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Multi-step ADC with sub-ADC calibration

A sub-analog-to-digital converter technology, used in analog/digital conversion calibration/testing, analog-to-digital converters, etc., can solve problems such as extra complexity, inability to solve static comparator offsets, and increasing the output voltage range of residual amplifiers

Active Publication Date: 2020-02-28
MAXIM INTEGRATED PROD INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, as the FLASH comparator shifts, timing and bandwidth errors increase the output voltage range of the residual amplifier
It has been demonstrated that timing and bandwidth errors can be calibrated; however this introduces additional complexity and does not account for static comparator offsets

Method used

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  • Multi-step ADC with sub-ADC calibration
  • Multi-step ADC with sub-ADC calibration
  • Multi-step ADC with sub-ADC calibration

Examples

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Embodiment Construction

[0022] In the following description, for purposes of explanation, specific details are set forth in order to facilitate the understanding of the present invention. It will be apparent, however, to one skilled in the art that the invention may be practiced without these details. Those skilled in the art will appreciate that the embodiments of the invention described below can be practiced in various ways and using various devices. Those skilled in the art will also recognize that additional modifications, applications, and embodiments are within the scope of the invention, as the invention may find utility in other fields. Accordingly, the following examples are illustrative of specific embodiments of the invention and are intended not to obscure the invention.

[0023] References in the specification to "one embodiment" or "an embodiment" mean that a specific feature, structure, characteristic or function described in connection with the embodiment is included in at least one...

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Abstract

The invention relates to a multi-step type analog-digital converter (ADC) with sub ADC calibration. According to the embodiments of the invention, error calibration of an existing analog-digital converter (ADC) with multiple cascaded ADC grades is performed. Information used in the calibration process is exchanged among the ADC grades. According to the embodiments, the calibration of one grade by using a feedback signal from at least one later grade is performed. According to part of the embodiments of the invention, the speed of the calibration process is increased by using rough and fine sub ADCs.

Description

technical field [0001] The present invention relates to analog-to-digital converters (ADCs), and more particularly to systems, apparatus and methods for providing calibration to multi-level ADCs. Background technique [0002] Multi-step ADCs are a known architecture for digitizing analog input signals and are generally preferred for high speed and high resolution applications. In a pipeline ADC, the task of quantizing an input signal is distributed among multiple stages. Each stage has: a sub-ADC to quantize the input signal, a DAC to subtract an estimate of the input signal, and a residual amplifier to amplify the difference to be further processed by subsequent stages. Together, the DAC and the residual amplifier are called a multiplying digital-to-analog converter (MDAC). The larger number of sub-ADC stages allows the use of high gain in the first stage, which eases the linearity requirements of the first-stage residual amplifier, reduces the number of stages, and signi...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M1/12H03M1/10
Inventor S·沈D-Y·张M·A·Z·斯特拉耶尔H-S·李
Owner MAXIM INTEGRATED PROD INC
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