Internal CRC (cyclic redundancy check) code FPGA (field programmable gate array) configuration file generation method

Abstract

The invention provides an internal CRC (cyclic redundancy check) code FPGA (field programmable gate array) configuration file generation method. The method includes the following steps: based on an FPGA configuration file generated by an EDA (electronic design automation) tool, reading FPGA configuration information included in the configuration file according to a characteristic value, and computing CRC codes corresponding to the configuration information by frame; searching for a blank area in the configuration file; writing the computed configuration frame CRC codes into the blank area obtained by searching so as to complete internal CRC code FPGA configuration file generation. Idle resources in the original FPGA configuration file are fully utilized, simultaneous same-place storage of FPGA check information and configuration information is realized on the basis of no extra software and hardware overhead, the computation process does not depend on a specific FPGA chip physical structure, convenience is brought to a hardware resource limited platform to realize read-back check of the FPGA configuration information so as to achieve the purpose of system fault tolerance, and the method has broad application prospect.

Description

technical field [0001] The invention relates to a method for generating an FPGA configuration file with a built-in CRC check code, and belongs to the technical field of reliability design of FPGA circuits. Background technique [0002] SRAM-type FPGAs have always been prone to errors due to their internal configuration registers being affected by single-event effects. When used in aerospace and other occasions that have high requirements for reliability, errors must be detected by reading back the configuration file. There are two common error detection methods for configuration files. One is to compare the full text bit by bit, and the other is to use the inherent configuration error detection resources inside the FPGA to verify the configuration information. Although the full-text comparison method is simple, it requires a large amount of external storage space for storing configuration files and corresponding mask files, and is not suitable for environments with limited ...

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Problems solved by technology

Since not all types of FPGAs are equipped with internal error detection resources, and the structure and function implementation of the resources are not disclosed, the reliability and safety of method 2 are difficult to verify, and the universality is not good

[0003] Due to the inherent reliability weakness of SRAM-type FPGAs, SRAM-type FPGAs have never been used in my country's space vehicle control computers, and the application of on-orbit error detection technology for SRAM-type FPGA configuration files is lacking, which greatly restricts the development of my country's space vehicle control computer technology. develop

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