Digital phase discriminator used for GPS tame crystal oscillator

Abstract

The invention discloses a digital phase discriminator used for a GPS tame crystal oscillator. The digital phase discriminator used for the GPS tame crystal oscillator comprises a 2N frequency divider, a high level pulse width counter, a low level pulse width counter, a pulse per second clock, a phase difference counter clock, a frequency count value latch and a phase error value latch. The 2N frequency divider is used for performing frequency division on 1 Hz PPS signals output by a GPS module. The high level pulse width counter and the low level pulse width counter are used for counting high level pulse widths and low level pulse widths. The pulse per second clock is in input connection with frequency locking enabled signals provided by the outside, is connected with the GPS and performs frequency diversion on inner pulse per second signals output by an OCXO clock. The phase difference counter clock inputs the inner pulse per second signals and PPS signals output by the GPS module, calculates the time difference of rising edges of the inner pulse per second signals and rising edges of the PPS signals, and outputs count values of the phase difference. The frequency count value latch and the phase error value latch are used for achieving the frequency at which an OCXO tracks GPS signals and the PPS signals and meanwhile output frequency values and phase error values. According to the digital phase discriminator used for the GPS tame crystal oscillator, time sequence design is facilitated, and the problem of lead-lag fuzziness of initial phase errors is avoided; the scheme of serial counters is adopted in the frequency counter and the phase measurement counter, so the frequency of the counter clock will not be affected by counting digits.

Description

technical field [0001] The invention belongs to the field of phase detectors, in particular to a digital phase detector used for GPS taming crystal oscillators. Background technique [0002] The digital phase detector is an essential part of the digital phase-locked loop. Its basic function is to measure the time difference between the input clock signal and the edge of the reference clock signal, reflect the phase difference, and output the leading phase value and the lagging phase according to the leading and lagging conditions. value. The commonly used digital phase detector is a double D flip-flop phase detector, and the output signal has an analog output mode in which the pulse width represents the phase difference; there is also a digital output mode in which a timing counter counts the time difference of the edge and outputs a digital quantity; the time difference of the timing edge is generally used High-speed clock counts to measure the time difference, and there i...

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Problems solved by technology

[0004] (1) The existing phase detector cannot directly measure the frequency deviation, but reflects the frequency deviation through the phase change difference, and the existing phase difference only measures the rising edge or the lower edge of the pulse signal, so that the frequency deviation measurement will be affected by the edge Influenced by jitter, measurement error increases

[0005] (2) In order to achieve high-precision frequency output in GPS taming active crystal oscillator applications, the signal used for phase detection requires a long period (above the second level), resulting in a very low sampling frequency for phase detection

High precision OCXO with high Q (up to 10 7 ), resulting in a very narrow voltage-controlled adjustable frequency range

The above two factors will lead to a slower adjustment speed of the PLL

Moreover, due to the randomness of the initial phase, when the existing double D fli

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