A low-trigger negative-voltage-resistant SCR device, process method, and application circuit

Abstract

The present invention is applicable to the field of semiconductor devices, and provides an SCR device with low trigger negative voltage resistance, a process method and an ESD application circuit. The device includes: a substrate, a first deep implant well formed in the substrate, and A first active region formed in a deep implant well; a second deep implant well formed in the substrate, a second active region formed in the second deep implant well, and a second deep implant well formed in the second deep implant well The first active region; the second well formed in the second deep implanted well, the first well formed in the second deep implanted well, the first well formed by simultaneous implantation into the two wells at the junction of the first and second wells An active region, a second active region formed in the first well, and a first active region formed in the first well. The negative-voltage-resistant SCR device with low trigger voltage provided by the invention can reduce the trigger voltage of the negative-voltage-resistant SCR device to below the breakdown voltage of the internal gate oxide layer of the chip, thereby realizing the design requirement of effective ESD protection.

Description

technical field [0001] The invention belongs to the field of semiconductor devices, in particular to an SCR device with low trigger negative voltage resistance, a process method and an ESD application circuit. Background technique [0002] Compared with other electrostatic protection (ESD) devices, silicon controlled rectifier (SCR) devices have higher protection performance per unit area due to their low holding voltage characteristics. [0003] figure 1 Shows the cross-sectional structure of an existing high trigger negative voltage withstand SCR device, the SCR device structure includes: a P-type substrate (PSUB) 1, a plurality of deep implanted P wells formed in the P-type substrate 1 by doping (DPWELL) 2, and the P+ active region (P+) 3 formed by doping in each deep implanted P well 2, the P type substrate 1 is grounded through the P+ active region 3 through the deep implanted P well 2; [0004] The SCR device structure also includes: a deep implanted N well (HDWELL) ...

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Problems solved by technology

[0010] The purpose of the embodiment of the present invention is to provide an SCR device with negative voltage resistance and low trigger voltage, aiming to solve the problem that the trigger voltage of the existing SCR device is higher than the breakdown voltage of the internal gate oxide layer of the chip, and cannot achieve effective ESD protection.

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