Expandable fpga display system, method and electronic device with microprocessor mcu
A microprocessor and display system technology, applied in the field of FPGA, can solve problems such as tight FPGA design timing, potential safety hazards, and changes in the output address of external memory, and achieve the effect of reducing potential safety hazards and improving utilization rate
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment 1
[0025] figure 2 It is a structural diagram of the FPGA with MCU in the embodiment of the present invention when the FIFO is fully asynchronous. in figure 2 In the embodiment of the present invention, the structure diagram when the FIFO is fully asynchronous includes: at least one first FIFO is an asynchronous FIFO, a logic module, a second asynchronous FIFO, an LCD module, an LCD address generator, and a state machine controller.
[0026] Expandable FPGA electronic equipment with microprocessor MCU, including the above-mentioned modules, MCU, external memory and display screen.
[0027] Specifically, the state machine controller makes the FPGA perform different operations on the external memory in different states. The states that the state machine controller needs to control include: idle state, that is, no operation; display output state, read data in the external memory for display output according to the empty and full states of the second asynchronous FIFO, so as to ensure t...
Embodiment 2
[0036] image 3 It is a structural diagram of the FPGA with MCU in the second embodiment of the present invention when the FIFO is synchronously shaped and synchronized. in image 3 In the MCU without clock, at least one of the first FIFOs is a synchronous shaping plus synchronous FIFO, and the system also includes at least two registers. After the registers perform synchronous shaping on the MCU data, the data is written into the synchronous FIFO. . Shaping refers to adjusting the input signal to a pulse signal according to the system clock. The signal received by FPGA first passes through multiple registers and samples the control signal and data from the slower clock domain multiple times and logically combines them to complete synchronous shaping and send the data to the first FIFO.
[0037] Taking the display method used in synchronous shaping and synchronous FIFO structure as an example, the modes of the external MCU are write single point, eight points, fill and move re...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More 


