Dynamic multi-selection-region division method based on FPGA (field programmable gate array) analytical layout solver

Abstract

The invention relates to a dynamic multi-selection-region division method based on an FPGA (field programmable gate array) analytical layout solver. The dynamic multi-selection-region division method comprises the following steps: constructing a first cost function based on connection relations between all basic units, forming LEs (logic elements), in a netlist, and calculating first coordinate values of all the LEs in a chip layout; determining a plurality of overlapped regions of the LEs in a chip, and finding out legal region ranges for the overlapped regions respectively; performing recursive secondary division on the overlapped regions in parallel; applying tension respectively to the LEs in the overlapped regions subjected to secondary division to pull the LEs in all the overlapped regions away; constructing a second cost function based on the connection relations between all the basic units of all the pulled-away LEs, and generating second coordinate values of all the LEs; continuously determining overlapped regions, finding out legal region ranges for the overlapped regions, and carrying out iteration to generate Nth coordinate values of the LEs until the Nth coordinate values are legal layout solutions of the LEs. According to the dynamic multi-selection-region division method, the parallel secondary division speed is high, and the calculation speed is greatly increased.

Description

technical field [0001] The invention relates to an FPGA layout algorithm, in particular to a method for dynamically dividing multi-choice regions based on an FPGA analytic layout solver. Background technique [0002] At present, in the application of FPGA (Field Programmable Gate Array, Field Programmable Logic Gate Array), integrated circuits are required to have a programmable or configurable interconnection network, and logic gates are connected to each other through a configurable interconnection network, as an independent chip Or the FPGA that plays a role in the core part of the system has been widely used in a large number of microelectronic devices. The broad definition of FPGA logic gates not only refers to simple NAND gates, but also refers to logic units with configurable functions of combinational logic and sequential logic or logic blocks composed of multiple logic units interconnected. [0003] With the expansion of the FPGA chip scale, the layout algorithm is...

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Problems solved by technology

[0005] However, the industry has not yet proposed a good solution to the overlapping problem of the analytical algorithm. Generally, in the first iteration, the solved LE coordinates overlap a lot, and the overlap between the LEs in the last iteration is the smallest, even if it is the last Iteration cannot completely eliminate the overlap between LEs. Generally, a partial legalization process is added after the analytical algorithm. Due to the large size of the layout circuit, the processing time is too long, which often fails to meet the program running time requirements.

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