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Design method of memory anti-multi-bit flip reliability evaluation model under the influence of negative bias temperature instability

A technology of negative bias temperature and instability, applied in static memory, instruments, etc., can solve the problem of low accuracy of model evaluation, and achieve the effect of improving accuracy

Active Publication Date: 2017-11-03
HARBIN INST OF TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0008] The present invention solves the problem of low evaluation accuracy of the model designed by the existing memory anti-multi-bit flip reliability evaluation model design method

Method used

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  • Design method of memory anti-multi-bit flip reliability evaluation model under the influence of negative bias temperature instability
  • Design method of memory anti-multi-bit flip reliability evaluation model under the influence of negative bias temperature instability
  • Design method of memory anti-multi-bit flip reliability evaluation model under the influence of negative bias temperature instability

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specific Embodiment approach 1

[0048] Specific implementation mode one: combine figure 1 Describe this embodiment, the design method of the memory anti-multi-bit flip reliability evaluation model under the influence of negative bias temperature instability,

[0049] Realized based on the following assumptions:

[0050] (1) The soft errors in the memory conform to the Poisson distribution;

[0051] (2) The probability of soft errors in the storage unit is uniformly distributed;

[0052] (3) At least two radiation events are required for the failure of the memory; when using ECC hardening technology, if the maximum number of error bits caused by an MBUs event in the memory is L, the ECC with the correction capability of L will be used; only when there are more than one word When an error occurs in the L bit, the memory will fail once;

[0053] (4) Two radiation events on a word are the main factors of memory failure; since the correction capability of ECC is the same as the maximum number of errors on a wo...

specific Embodiment approach 2

[0089] Specific embodiment two: formula (10) (11) described in this embodiment and effective boundary condition of formula (14) are respectively:

[0090]

[0091]

[0092] Among them, β is the probability that two radiation events produce more flipping digits than L; β nonscrubbing is β without erasing technique, β scrubbing is β using the erasure technique.

[0093] Other steps are the same as in the first embodiment.

specific Embodiment approach 3

[0094] Specific Embodiment Three: The memory described in this embodiment is a memory manufactured by a CMOS process below 65nm.

[0095] Other steps are the same as in the second embodiment.

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Abstract

The invention relates to a design method of a reliability evaluation model of a memory under the influence of negative bias temperature instability, which relates to the field of anti-radiation hardened circuits, and specifically relates to a design method of a reliability evaluation model of a memory under the effect of multi-bit flips. In order to solve the problem of low evaluation accuracy of the model designed by the existing memory anti-multi-bit flip reliability evaluation model design method. The present invention analyzes the influence of the NBTI effect on the critical charge, and obtains the corresponding value and corresponding relationship between the NBTI effect and the critical charge; counts EventSBU and EventMBU, and obtains the probability of MBUs events occurring in memories with different critical charges; according to the relationship between the MBUs event probability and the NBTI stress time Relational curve, establish a multi-bit flip event probability model considering the NBTI effect, and finally obtain a memory anti-multi-bit flip MTTF model considering NBTI effect without erasing technology and a memory anti-multi-bit flip MTTF model considering NBTI effect using erasing technology The invention is applicable to the field of anti-radiation reinforced circuits.

Description

technical field [0001] The invention relates to the field of anti-radiation hardened circuits, in particular to a method for designing a reliability evaluation model of a memory under the effect of multi-bit inversion. Background technique [0002] Soft errors caused by single-event upset effects are one of the severe challenges in the reliability design of integrated circuits for aerospace applications. When space radiation particles bombard the sensitive nodes of its memory, additional electron-hole pairs will be generated. If the charge accumulates to a certain extent beyond a critical value, that is, the critical charge, the logic value of the memory cell will be reversed, and a soft error will occur, which in turn will cause the electron System failure, spacecraft function failure, etc. Single event upset includes single bit upset (SBU) and multiple bit upset (MBUs), using error correction code (error correction code, ECC) is an effective means to protect memory agains...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C29/42
Inventor 肖立伊柳姗姗曹雪兵王天琦叶蓉
Owner HARBIN INST OF TECH
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