SRAM memory cell array, SRAM memory and control method of memory

Abstract

The invention provides an SRAM memory cell array, an SRAM memory and a control method of the memory. The SRAM memory cell array includes: a plurality of word lines arranged along a row direction, bit lines arranged along a column direction and a plurality of memory cells positioned between the word lines and the bit lines, wherein the bit lines include a first bit line and a second bit line; a first read transistor and a second read transistor; and a first read bit line and a second read bit line, wherein the first read bit line and the second read bit line are respectively connected to the first bit line and the second bit line through the first read transistor and the second read transistor. The SRAM memory cell array has the advantages of improved stability and reduced size, so the size of an SRAM chip is reduced.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to an SRAM memory cell array, an SRAM memory with the SRAM memory cell array, and a control method for the SRAM memory. Background technique [0002] With the continuous development of digital integrated circuits, on-chip integrated memory has become an important part of digital systems. SRAM (Static Random Access Memory) has become an indispensable and important part of on-chip memory due to its advantages of low power consumption and high speed. SRAM can hold data as long as it is powered, there is no need to constantly refresh it. [0003] The overall structure of SRAM can be divided into two parts: memory cell array and peripheral circuit. In SRAM, the storage unit is the most basic and important component. The number of memory cells included in the array and the stability of the memory cells are two important factors affecting the performance of the SRAM. The la...

AI Technical Summary

Problems solved by technology

However, in the 6T structure SRAM, the data storage node is directly connected to the bit line through the transfer transistor. During the read process, due to the voltage division effect between the transfer transistor and the pull-down transistor, the data of the storage node will be disturbed. In addition, the storage node’s Data is also easily affected by external noise which may cause logic errors and affect the stability of memory cells

Although the double-terminal SRAM memory cell of the 8T structure improves the stability of the memory cell, compared with the SRAM memory cell of the 6T structure, the number of transistors increases, and the size of the memory cell array increases accordingly, which is not conducive to the integration of integrated circuits. improvement and miniaturization of chip size

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