Unlock instant, AI-driven research and patent intelligence for your innovation.

Timing adjustment circuit and semiconductor integrated circuit device

A timing adjustment, circuit technology, applied in the direction of electrical components, single output arrangement, automatic power control, etc., can solve problems such as difficulty in generating timing adjustment output signals and narrowing of the PFD operating range.

Active Publication Date: 2015-05-20
SOCIONEXT INC
View PDF19 Cites 2 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] In other words, when the frequency of the input signal (input clock signal) of the DLL circuit becomes higher, the operable range of the PFD narrows, so, for example, the PFD malfunctions at startup, which may make it difficult to generate timing-adjusted output signal

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Timing adjustment circuit and semiconductor integrated circuit device
  • Timing adjustment circuit and semiconductor integrated circuit device
  • Timing adjustment circuit and semiconductor integrated circuit device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0034] First, before describing the embodiments of the timing adjustment circuit and the semiconductor integrated circuit device, reference will be made to Figures 1 to 6C An example describing a timing adjustment circuit and its problematic points.

[0035] figure 1 is a block diagram depicting an example of a timing adjustment circuit (DLL circuit). exist figure 1 , reference numeral 1 denotes a voltage-controlled delay line (VCDL), reference numerals 101 to 112 denote delay units, and reference numerals 203 to 211 denote waveform shaping units. Further, reference numeral 3 denotes a phase frequency detector (PFD: Phase Detector), reference numeral 4 denotes a charge pump (CP), and reference numeral 5 denotes a capacitor.

[0036] Such as figure 1 As depicted in , VCDL 1 has a plurality of cascaded delay units 101 to 112, and the output signals of delay units 103 to 111 are output via corresponding waveform shaping units 203 to 211, respectively.

[0037] For example, ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

A timing adjustment circuit includes a voltage-controlled delay line, a phase detector, a control voltage generation circuit, and a startup circuit. The voltage-controlled delay line receives an input clock signal and generates multi-phase clocks, a delay amount of each of the multi-phase clocks is changed according to a control voltage. The phase detector detects a phase difference between a first clock and a second clock, the first clock is a reference, the second clock is generated from the voltage-controlled delay line. The control voltage generation circuit generates the control voltage on the basis of the detected phase difference. The startup circuit operates for a certain period after activation, and continuously changes the control voltage between a first voltage and a second voltage.

Description

technical field [0001] Embodiments discussed herein relate to timing adjustment circuits and semiconductor integrated circuit devices. Background technique [0002] In recent years, the performance of semiconductor memories (for example, DRAM: Dynamic Random Access Memory), processors, and the like used in computers and other information processing devices has been significantly improved. Therefore, it is preferable to correctly and promptly carry out signal transmission between chips mounted on a circuit board and between a plurality of elements and circuit blocks within a chip. [0003] In view of this, for example, there is a known technique in which: a timing adjustment circuit (for example, DLL circuit: Delay Locked Loop circuit) is provided on the receiving side; a multi-phase clock is generated by delaying an input clock signal passing through the DLL circuit ; and read (determine) data at an appropriate timing. [0004] On the other hand, there is also a known SerD...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H03L7/08H03K5/14
CPCH03L7/0807H03L7/0812H03L7/10H03L7/085
Inventor 松田笃
Owner SOCIONEXT INC