System and method for testing performance of Ethernet

Abstract

The invention discloses a system for testing the performance of an Ethernet. The system is implemented by an FPGA programmable logic device and comprises a sending side logic and a receiving side logic, wherein the sending side logic comprises a packet assembling module and a scheduling module; the scheduling module generates a packet assembling enabling signal; the packet assembling module assembles a corresponding type of a data packet according to the packet assembling enabling signal generated by the scheduling module based on the type of a packet and whether a label is added or not and sends the data packet; an MAC receives the data packet sent by the sending side logic, controls the flow and then performs outputting; the receiving side logic comprises an unpacking module and a counting module; the unpacking module receives the data packet sent by the MAC, analyzes the data packet and tests the performance of the Ethernet according to information of the label; the counting module counts information of the received data packet, analyzes the label and counts a normal packet, a repeated packet, a disorder packet, the number of lost packets and the number of bites and the phenomena of time delay and shaking. The system has the advantages that the data packet is convenient to analyze, and the efficiency of testing the network performance is improved.

Description

technical field [0001] The invention belongs to the field of communication testing and relates to a system and method for testing Ethernet performance. Background technique [0002] Ethernet performance testing mainly includes: bit error rate test, which is to send a test pattern in the entire Ethernet-based circuit, and then compare the number of wrong bits with the number of bits sent to measure the bit error rate; frame loss test, It is to calculate the percentage of the number of frames that should be forwarded but not forwarded by the network device due to lack of resources in a steady state (normal state); delay test, which is to measure the last bit of the input frame arriving at the input port and seeing it on the output port The time interval between the first bits of output frames. [0003] It can be seen from the prior art that the traffic is analyzed during the test, and the frame is not decorated. The obvious disadvantage is that when testing some performance o...

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Problems solved by technology

[0003] It can be seen from the prior art that the traffic is analyzed during the test process, and the frames are not decorated. The obvious disadvantages brought about by this are: when testing some performances of Ethernet, the packets lack of recognition and it is difficult to comprehensively analyze them. Network performance, such as when testing packet loss / out-of-sequence repeated packets, it is impossible to locate specific packets, and there are large errors in delay and jitter

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