System and method for testing performance of Ethernet

An Ethernet and performance technology, applied in the system field of testing Ethernet performance, can solve problems such as difficulty in comprehensively analyzing network performance, delay and jitter error, lack of packet identification, and achieve simple structure, improved efficiency, and wide application. Effect

Inactive Publication Date: 2015-05-27
OPWILL TECH BEIJING
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] It can be seen from the prior art that the traffic is analyzed during the test process, and the frames are not decorated. The obvious disadvantages brought about by this are: when testing some performances of Ethernet, the packets lack of

Method used

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  • System and method for testing performance of Ethernet
  • System and method for testing performance of Ethernet
  • System and method for testing performance of Ethernet

Examples

Experimental program
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Embodiment 1

[0021] Please refer to figure 1 , the system for testing Ethernet performance of the present invention is realized by FPGA programmable logic devices, including: sending side logic, including a group packet module and a scheduling module, and the scheduling module is used to generate an enabling signal for group packet; Packing module, used to generate the enabling signal of grouping according to the scheduling module, according to the type of the package and whether to add a label (by software configuration-enabling signal, enabling signal is valid, adding label; enabling signal is invalid, not adding label ), forming a corresponding type of data packet and sending it; MAC, used to receive the data packet sent by the sending side logic, and control the flow, and then output it; the receiving side logic includes an unpacking module and a statistics module, The unpacking module is used to receive the data packets sent from the MAC, parse the data packets, and test the Ethernet ...

Embodiment 2

[0046] Please refer to figure 2 , the present embodiment provides a method for testing Ethernet performance, implemented by an FPGA programmable logic device, including: sending side logic, including a grouping module and a scheduling module, and the scheduling module is used to generate an enabling signal for grouping , and after receiving the feedback signal sent by the grouping module, send the information of the grouping module to the grouping module; type and whether to add a label to form a data packet of the corresponding type and send it; MAC receives the data packet sent by the logic on the sending side, controls the flow, and then outputs it; the logic on the receiving side includes an unpacking module and statistics module, the unpacking module receives the data packet sent from the MAC, analyzes the data packet, and tests the Ethernet performance through the information of the label; the statistical module counts the information of the received data packet, and an...

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Abstract

The invention discloses a system for testing the performance of an Ethernet. The system is implemented by an FPGA programmable logic device and comprises a sending side logic and a receiving side logic, wherein the sending side logic comprises a packet assembling module and a scheduling module; the scheduling module generates a packet assembling enabling signal; the packet assembling module assembles a corresponding type of a data packet according to the packet assembling enabling signal generated by the scheduling module based on the type of a packet and whether a label is added or not and sends the data packet; an MAC receives the data packet sent by the sending side logic, controls the flow and then performs outputting; the receiving side logic comprises an unpacking module and a counting module; the unpacking module receives the data packet sent by the MAC, analyzes the data packet and tests the performance of the Ethernet according to information of the label; the counting module counts information of the received data packet, analyzes the label and counts a normal packet, a repeated packet, a disorder packet, the number of lost packets and the number of bites and the phenomena of time delay and shaking. The system has the advantages that the data packet is convenient to analyze, and the efficiency of testing the network performance is improved.

Description

technical field [0001] The invention belongs to the field of communication testing and relates to a system and method for testing Ethernet performance. Background technique [0002] Ethernet performance testing mainly includes: bit error rate test, which is to send a test pattern in the entire Ethernet-based circuit, and then compare the number of wrong bits with the number of bits sent to measure the bit error rate; frame loss test, It is to calculate the percentage of the number of frames that should be forwarded but not forwarded by the network device due to lack of resources in a steady state (normal state); delay test, which is to measure the last bit of the input frame arriving at the input port and seeing it on the output port The time interval between the first bits of output frames. [0003] It can be seen from the prior art that the traffic is analyzed during the test, and the frame is not decorated. The obvious disadvantage is that when testing some performance o...

Claims

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Application Information

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IPC IPC(8): H04L12/26
Inventor 朱天全鲍胜青鲍丽娜
Owner OPWILL TECH BEIJING
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