Accurate high-capacity packet counting method for 100G interfaces

Abstract

The invention relates to an accurate high-capacity packet counting method for 100G interfaces. The accurate high-capacity packet counting method comprises the following steps: (A) completing high bit position counting storage of table item storage by an external storage device, self-building a few of storage spaces inside a logic device, and counting the low bit positions of number of packets and number of bytes in each table item; (B) after counting preprocessing, dividing into a plurality of sub-modules for operation. The accurate high-capacity packet counting method for 100G interfaces disclosed by the invention is characterized in that two tables need to be maintained, the read-write bandwidth required by counting becomes extremely large due to the problem of 100G bandwidth, so that the similar counting is maintained inside but only the lowest several bit widths are recorded so as to eliminate frequent operation for off-chip storage, the using number of block random access memories (BRAM) inside an FPGA is reduced, the device cost is reduced, the read-write operation of external storage becomes slow and can be completed by using a low-cost synchronous dynamic random access memory (SDRAM), and the bandwidth needed for 100G counting is sufficiently supported.

Description

technical field [0001] The invention relates to the technical field of digital communication, in particular to a large-capacity and accurate packet counting method for a 100G interface. Background technique [0002] On June 17, 2010, the Institute of Electrical and Electronics Engineers (IEEE) officially approved the IEEE 802.3ba standard. In 2013, domestic operators began to fully deploy 100G transmission networks, and equipment connected to 100G networks relied on the After analyzing all kinds of traffic, the statistics of the set table items are obtained. The 100G bandwidth is 10 times the speed of the original common network interface, which brings the demand for statistical speed to increase by 10 times. The traditional large-scale static random access memory (SRAM) statistics method The interface rate is no longer sufficient. [0003] The front-end dedicated interface processing chip (or field programmable gate array (FPGA) internal 100G interface module is connected ...

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Problems solved by technology

[0002] On June 17, 2010, the Institute of Electrical and Electronics Engineers (IEEE) officially approved the IEEE 802.3ba standard. In 2013, domestic operators began to fully deploy 100G transmission networks, and equipment connected to 100G networks relied on the After analyzing all kinds of traffic, the statistics of the set table items are obtained. The 100G bandwidth is 10 times the speed of the original common network interface, which brings the demand for statistical speed to increase by 10 times. The traditional large-scale static random access memory (SRAM) statistics method The interface rate can no longer be satisfied

External storage at such a rate is no longer acceptable, or some people doubt that there is a static random access memory (SRAM) inside the logic device, which can be completed with internal storage, but the internal resources of the FPGA are limited, and it is currently used for core devices such as routers. The storage bit width of the byte and packet length statistics is 64 bits, and the current session capacity is more than 256K. After calculation, the storage capacity is 32M. It can be seen from the resource table of our mainstream XILINX Kintex 7 logic chip, the minimum The 7K70T has only 4M block access memory (BRAM)

[0007] Even if it is a relatively large device, if it is only used to complete the statistical function alone, the cost will be huge, which will directly affect the market competitiveness of the product

[0008] Moreover, it is well known that the price and storage capacity of static random access memory (SRAM) are not comparable to those of dynamic random access memory (DRAM). Even if the latest HMC (Hybrid Memory Cube, hybrid memory cube) is used, the price is extremely high and it takes Parallel-serial and serial-parallel converter (serdes) resources of logic chips, the main factors of the price of logic chips are parallel-serial and serial-parallel converters (serdes), internal wiring resources, followed by capacity and parallel IO interface Quantity, and the interface rate of 100G bandwidth According to the previous analysis, directly use the quadruple data rate static random access memory (QDR)-static random access memory (SRAM), the required interface rate brings circuit board wiring, power consumption, chip cost The increase in the accuracy of statistics is not worth the loss. Whether it is possible to use low-cost devices to complete the accurate statistics of large-capacity rule hits. In core functions such as device networking, security filtering, and route conversion, accurate statistics of interfaces are required to provide Analysis of Upward Strategies

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