Method of forming a transistor

A transistor and dry cleaning technology, used in semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve problems such as unclean removal of dummy gate 02, improve etching effect, avoid pollution, and achieve good results

Active Publication Date: 2017-08-25
SEMICON MFG INT (SHANGHAI) CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The dummy gate 02 is usually formed of polysilicon. In the prior art, a combination of anisotropic dry etching and wet etching is generally used to remove the dummy gate 02 made of polysilicon. However, in the prior art, when removing the dummy gate 02 , there is a problem that the removal of the dummy gate 02 is not clean, and polysilicon residue 07 is formed at the bottom of the opening formed by removing the dummy gate (such as figure 2 shown)

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  • Method of forming a transistor
  • Method of forming a transistor

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Embodiment Construction

[0034] After dry etching removes most of the dummy gates in the dummy gate structure, pollutants such as particles and organic matter will be produced on the surface of the remaining dummy gates, and polymer particles and oxide layers, etc., will seriously affect the subsequent process. Particles and oxide layer adhere to the surface of the residual dummy gate. Due to the strong selectivity of the subsequent wet etching, the residual dummy gate blocked by polymer particles and oxide layer is difficult to be etched clean, and it is easy to make the final formed Transistors develop defects.

[0035] In order to wet-etch the pseudo-gate dielectric layer with pseudo-gate residues and other pollutants on the surface, the concentration of the etching solution used is relatively high, and the high-concentration etching solution is easy to corrode the interlayer dielectric layer.

[0036] In order to solve the above technical problems, the present invention provides a method for formi...

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Abstract

The present invention provides a method for forming a transistor, comprising: providing a substrate; forming a dummy gate structure including a dummy gate on the surface of the substrate; forming a source region and a drain region in the substrate exposed by the dummy gate structure; An interlayer dielectric layer flush with the dummy gate structure is formed on the substrate; most of the dummy gates in the dummy gate structure are removed by dry etching; first dry cleaning is performed on the remaining dummy gate surface ; Wet cleaning the surface of the remaining dummy gate; Carrying out a second dry cleaning on the surface of the remaining dummy gate; Wet etching removes the remaining dummy gate to form an opening corresponding to the shape of the dummy gate; forming a gate in the opening Dielectric layer and metal gate. Through the steps of first dry cleaning, wet cleaning and second dry cleaning, the residual pollutants on the surface of the dummy gate after dry etching the dummy gate are removed, so as to optimize the performance of the transistor.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a method for forming a transistor. Background technique [0002] In the high-K dielectric / metal gate engineering of transistors, after high-temperature annealing for ion activation, dummy gates such as polysilicon gates need to be removed, and then filled with metal gate electrodes to form a high-K dielectric / metal gate structure. [0003] refer to figure 1 and figure 2 , shows a method for forming a transistor in the prior art. Such as figure 1 As shown, the shallow trench isolation region 08 is formed in the substrate 01, the dummy gate structure of the NMOS transistor is formed on the left side of the shallow trench isolation region 08, and the dummy gate structure of the PMOS transistor is formed on the right side, and each dummy gate structure Including a gate dielectric layer 03, a capping layer 06, and a dummy gate 02, the sidewall of the dummy gate structure is also pro...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H01L21/28
Inventor 曾以志赵杰宋伟基
Owner SEMICON MFG INT (SHANGHAI) CORP
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