VDMOS field effect transistor and forming method thereof

Abstract

Disclosed are a VDMOS field effect transistor and a forming method thereof. The method includes providing a substrate provided with a first type dopant; forming first and second grooves in the substrate; forming a first insulation layer on the side wall of the first groove, and forming a second insulation layer on the side wall of the second groove; filling the first groove with a first polycrystalline silicon layer with the second type dopant, and filling the second groove with a second polycrystalline silicon layer with the second type dopant; forming a first buried layer with the second type dopant on the substrate below the first polycrystalline silicon layer, and forming a second buried layer with the second type dopant on the substrate below the second polycrystalline silicon layer; forming a first well region on the substrate between the first and second polycrystalline silicon layers in a doped manner; forming a second well region on the first well region; forming a first gate electrode on the first well region; forming a first source electrode on the second well region and forming a first leakage electrode on the upper surface of the first polycrystalline silicon layer. By the aid of the telescopic scheme, the extension growing process is omitted, and cost is low.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a VDMOS field effect transistor and a forming method thereof. Background technique [0002] As a kind of power device, Vertical Double-diffused Metal-Oxide Semiconductor (VDMOS) field effect transistor is widely used due to its advantages of high input impedance and low conduction voltage drop. [0003] refer to figure 1 , existing VDMOS FETs include: [0004] A substrate 1 with N+ doping, the substrate 1 includes a front side S1 and a back side S2; [0005] An epitaxial layer 2 with N+ doping located on the front side S1 of the substrate 1; [0006] A gate dielectric layer 3 on the epitaxial layer 2 and a gate 4 on the gate dielectric layer 3; [0007] The P well region 5 located in the epitaxial layer 2 around the gate 4 and the source 6 located in the P well region 5, the source 6 is close to the gate 4, and the P well region 5 partially extends under the gate diele...

AI Technical Summary

Problems solved by technology

[0011] The problem solved by the present invention is that the epitaxial layer growth process in the existing VDMOS field effect transistor is complicated and the cost is high

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