Thin film transistor array substrate and preparation method thereof, display device

A technology for thin film transistors and array substrates, applied in the display field, can solve the problems of gate transfer electrostatic discharge, gate easily corroded, and high production cost of mask plates, so as to reduce the risk of gate corrosion and reduce production costs. Effect

Active Publication Date: 2015-06-10
BOE TECH GRP CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0014] The purpose of the present invention is to solve the problems of thin-film transistor array substrate and its preparation method in the prior art, many masks in the preparation of the display device, high production cost, easy corrosion of the grid, and electrostatic discharge of the grid transfer.

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  • Thin film transistor array substrate and preparation method thereof, display device
  • Thin film transistor array substrate and preparation method thereof, display device
  • Thin film transistor array substrate and preparation method thereof, display device

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Embodiment 1

[0052] Such as Figure 5As shown, this embodiment provides a thin film transistor array substrate, including: a display area and a frame area surrounding the display area, wherein the display area includes:

[0053] The substrate 1 and the gate electrode 2, the first insulating layer 3, the active layer 4, the etch stop layer 5, the source and drain electrodes 6, the second insulating layer 7 and the pixel electrode 8 formed sequentially on the substrate 1, in the The pattern of the second insulating layer 7 in the display area is the same as that of the etching stopper layer 5 .

[0054] In this embodiment, the same mask is used to prepare the second insulating layer 7 and the etching stopper layer 5, which saves a mask and reduces production costs; at the same time, the second insulating layer in the display area The pattern of the layer 7 is the same as that of the etching barrier layer 5, which ensures that the pixel electrode 8 is connected to the drain through the via h...

Embodiment 2

[0061] This embodiment provides a method for preparing the above-mentioned thin film transistor array substrate, which includes forming various functional layers in the display area of ​​the thin film transistor array substrate and the frame area surrounding the display area by adopting the following steps: specifically,

[0062] Such as Figure 8 As shown, a gate 2 is formed on a substrate 1 through a patterning process, and a gate mask can be used in this step;

[0063] Such as Figure 9 As shown, the first insulating layer 3 (gate insulating layer) is deposited on the substrate 1 forming the gate 2; the first insulating layer mask is used in this step (referred to as 6-mask process at this time), also If this step is not used, it is called a 5-mask process.

[0064] Such as Figure 10 As shown, the active layer 4 is formed on the substrate 1 on which the first insulating layer 3 is deposited by a patterning process, and an active layer mask is used in this step;

[0065...

Embodiment 3

[0080] This embodiment provides a display device, which includes the above thin film transistor array substrate.

[0081] The thin-film transistor array substrate and the preparation method thereof of the present invention, and the display device use the same mask plate when preparing the second insulating layer 7 and the etching stopper layer 5, which saves a mask plate and reduces the production cost; at the same time , in the display area, the pattern of the second insulating layer 7 is the same as that of the etching stopper layer 5, which ensures that the pixel electrode 8 is connected to the drain through the via hole; in the frame area, the source and drain electrodes 6 directly cover the When the gate 2 and the source and drain 6 are made of corrosion-resistant metals, the risk of corrosion of the gate 2 and the risk of electrostatic discharge of the transfer of the gate 2 can be reduced.

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Abstract

The invention provides a thin film transistor array substrate and a preparation method thereof, and a display device, belongs to the technical field of display, and aims at solving the problems of high production cost due to more mask plates in preparation, corrosion of a grid electrode, and electrostatic discharge in adapting of a grid electrode of the existing thin film transistor array substrate and the preparation method, and the display device. According to the existing thin film transistor array substrate and the preparation method, and the display device, the same mask plate is adopted while preparing a second insulating layer and an etching resisting layer, so that one mask plate can be saved, and as a result, the production cost can be reduced; meanwhile, the second insulating layer has the same graph as the etching resisting layer in a display area, and therefore, a pixel electrode is connected with a drain electrode through a through hole; a source electrode and the drain electrode in the side frame area directly cover the grid electrode; when the source electrode and the drain electrode are manufactured from anticorrosion metal, the risk of corrosion of the grid electrode can be reduced, and the risk of electrostatic discharge in adapting of the grid electrode can be also reduced.

Description

technical field [0001] The invention belongs to the field of display technology, and in particular relates to a thin film transistor array substrate, a preparation method thereof, and a display device. Background technique [0002] Oxide thin film transistors have the advantages of high electron mobility, good uniformity of characteristics, relatively simple process, and large area, and are regarded as a new generation of thin film transistor display technology. At present, a 6-mask process is commonly used to prepare a thin film transistor array substrate, including sequentially preparing on a substrate 1: gate 2, first insulating layer 3, active layer 4, etch stop layer 5, source and drain 6 , the second insulating layer 7 and the pixel electrode 8; in order to improve product reliability and yield, a 7-mask process also appeared (an additional first insulating layer mask). However, the above-mentioned 6-mask or 7-mask process has the problem of a large number of masks an...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/02H01L29/786H01L21/34H01L21/82
Inventor 高山王杨
Owner BOE TECH GRP CO LTD
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