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Method for forming metal gate

A technology of metal gate and dummy gate, which is applied in the direction of electrical components, circuits, semiconductor devices, etc., can solve the problems of high process cost and complicated manufacturing process, and achieve the effect of simplifying process and saving process cost

Active Publication Date: 2017-12-29
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0009] As can be seen from the above description, the existing metal gate formation method needs to use different metal materials to form metal layers with different work functions, so the manufacturing process is complicated and the process cost is high.
[0010] For this reason, need a kind of new forming method of metal gate, in order to prevent from overcoming the problems of complex manufacturing process and high process cost of existing method

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  • Method for forming metal gate
  • Method for forming metal gate
  • Method for forming metal gate

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Embodiment Construction

[0043]Since the threshold voltages of the PMOS transistor and the NMOS transistor are different, the PMOS transistor and the NMOS transistor need to use metal layers with different work functions. The existing metal gate formation method is to form metal layers with different work functions through different metal materials. Therefore, the existing metal gate formation method needs to separately perform the formation process of the work function metal layer on the PMOS transistor and the NMOS transistor. As a result, the method for forming the metal gate is complex in process and high in process cost.

[0044] Compared with NMOS transistors, PMOS transistors require a metal layer with a larger work function. To this end, the present invention provides a method for forming a metal gate. After the forming method forms a barrier layer and a high-K gate dielectric layer on the PMOS region and the NMOS region, the barrier layer and the high-K gate dielectric layer on the PMOS regio...

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Abstract

A method for forming a metal gate comprises the following steps: providing a semiconductor substrate which has a PMOS region and an NMOS region, wherein a first high-K gate dielectric layer, a first barrier layer and a first dummy gate are formed in the PMOS region from bottom to top, a second high-K gate dielectric layer, a second barrier layer and a second dummy gate are formed in the NMOS region from bottom to top, and the semiconductor substrate further has an interlayer dielectric layer; removing the first dummy gate to form a first trench; performing gas annealing on the first barrier layer and the first high-K gate dielectric layer; removing the second dummy gate to form a second trench; forming work function metal layers on the bottoms and side walls of the first trench and the second trench; and filling the first trench and the second trench with metal material. By adopting the method, the manufacturing process is simplified, and the process cost is reduced.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a metal gate. Background technique [0002] The main device in an integrated circuit, especially a VLSI, is a metal oxide semiconductor field effect transistor (MOS transistor for short). Since the MOS tube was invented, its geometric size has been continuously reduced. In this situation, various limitations and technical challenges begin to appear, and further reduction in device size is becoming more and more difficult. As the manufacturing process of Complementary Metal-Oxide-Semiconductor (CMOS, Complementary Metal-Oxide-Semiconductor) shrinks to a level below 32nm, technologies using new designs and materials are introduced. In the fabrication of MOS transistor devices and circuits, the most challenging thing is the high gate leakage current caused by the reduction in the thickness of the gate structure formed by polysilicon and silicon oxide...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/28
CPCH01L29/401
Inventor 张海洋张城龙
Owner SEMICON MFG INT (SHANGHAI) CORP