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Method for forming fin field effect transistor

A fin field effect and transistor technology, which is applied in the fields of semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve the problems of poor performance of fin field effect transistors, and achieve the effect of improving performance

Active Publication Date: 2018-10-16
SEMICON MFG INT (SHANGHAI) CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0007] The problem solved by the present invention is that the performance of fin field effect transistors in the prior art is relatively poor

Method used

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  • Method for forming fin field effect transistor
  • Method for forming fin field effect transistor
  • Method for forming fin field effect transistor

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Experimental program
Comparison scheme
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Embodiment Construction

[0040] The reasons for the relatively poor performance of fin field effect transistors (FinFETs) in the prior art are as follows:

[0041] After the gate structure is formed, when ion implantation is performed on the fins on both sides of the gate structure to form the source and drain, the ion implantation process will convert the single crystal silicon in the fin 12 into amorphous silicon. The continuation of the implantation process will greatly increase the thickness of the amorphous silicon layer, and in severe cases, the inside of the fin portion 12 will become amorphous silicon. Compared with single crystal silicon, the grain size of amorphous silicon is not uniform, and the arrangement is disorderly. Therefore, the resistance value of the fin composed of amorphous silicon is relatively large. In addition, it is also difficult to determine the resistance or other physical properties of the fins composed of amorphous silicon, which makes it difficult to control the overa...

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Abstract

A forming method of a fin type field effect transistor comprises the following steps: providing a substrate having a first fin portion; forming a grid electrode spanning first fin portion, wherein the grid electrode partially covers the top and the lateral wall of the first fin portion; forming a protective layer covering the substrate and the grid electrode; forming a patterned mask layer on the protective layer, wherein the patterned mask layer exposes the protective layer at the first fin portion; removing the protective layer and the patterned mask layer covering the first fin portion in a same technology to form a patterned protective layer, wherein the patterned protective layer exposes the first fin portion and the grid electrode thereon; heating the substrate, then using the patterned protective layer as a mask to inject ions into the first fin portions on bilateral sides of the grid electrode, thereby forming a source electrode and a drain electrode; removing the patterned protective layer. By utilizing the method, the content of amorphous silicon in the ion injected first fin portion is reduced by a certain degree, or the amorphous silicon layer is thinned by a certain degree, accordingly improving the performance of the subsequently formed first fin type field effect transistor.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a method for forming a fin field effect transistor. Background technique [0002] With the development of the semiconductor industry to lower technology nodes, the transition from planar CMOS transistors to three-dimensional FinFET (3D Fin Field Effect Transistor) device structures has gradually begun. In FinFET, the gate structure can control the channel from at least two sides, which has a much stronger gate-to-channel control ability than planar MOSFET devices, and can well suppress the short-channel effect. And compared with other devices, it has better compatibility with the existing integrated circuit production technology. [0003] For the structure of the existing Fin Field Effect Transistor (FinFET), please refer to figure 1 , including: a semiconductor substrate 10; a buried oxide layer (BOX, Buried Oxide) 11 located on the semiconductor substrate 10; a raised structure ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336
CPCH01L29/66795
Inventor 何其暘张翼英
Owner SEMICON MFG INT (SHANGHAI) CORP