A Method of Measuring AC Interference Amplitude
A technology of AC interference and amplitude, applied in the direction of measuring current/voltage, measuring device, measuring electrical variables, etc., can solve the problem of low measurement accuracy, and achieve the effect of wide measurement range and easy integration
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Embodiment 1
[0044] Such as figure 1 , figure 2 and image 3 As shown, 23 inverters are cascaded into a loop to obtain a ring oscillator; a direct current is passed to the ring oscillator, and the relationship between the oscillation frequency and voltage is measured, and the following is obtained: Figure 4 curve shown; set nominal supply voltage V 0 , using the formula and Calculate the normalized offset NFS of the operating frequency of the ring oscillator at this voltage and the magnitude of the AC disturbance A RFI relationship, get as Figure 5 The curve shown; where V k The derivation process is as follows:
[0045] Such as Figure 6 Shown are nominal voltages V 0 and AC interference under test The superimposed image, with △ V DD Divide the measured interference into 2m intervals for the step size of the voltage value, and use k to represent the ordinal number of the interval after division, then the voltage peak value of the kth interval V kk (correspond Fig...
Embodiment 2
[0050] Such as Figure 8 and Figure 9 As shown, 1601 SMIC 130nm process INVX1 small inverters whose performance is shown in Table 1 are cascaded into a ring oscillator to drive a SMIC 130nm process INVX32 large inverter to form a sensing IP. The output end of this IP is connected through chip pads and package pins, connected to the frequency measuring instrument, and the operation according to the method described in Embodiment 1 can monitor the AC interference of the on-chip power network where the IP is located, thereby measuring Amplitude of AC interference. The performance index of such sensing IP is shown in Table 2. It can be seen that the area and power consumption of this IP are very small, which is suitable for implanting chips.
[0051] Table 1
[0052] gate parasitic delay
load factor
input capacitance
Gate power consumption
door area
0.0197 ns
4.8307 ns / pF
0.0026 pF
0.0032μW / MHz
3.69×0.92 μm 2
[0053] Tabl...
Embodiment 3
[0056] Such as Figure 10 and Figure 11 As shown, 1,000,001 SMIC 130nm process INVX1 small inverters whose performance is shown in Table 1 are cascaded into a ring oscillator to drive a SMIC 130nm process INVX32 large inverter to form a complete chip. The power supply of the dedicated chip is connected to the position of the circuit board to be observed, the output terminal of the chip is connected to the frequency measuring instrument, and the AC interference of the power supply network on the dedicated position can be monitored according to the method described in Embodiment 1. , so as to measure the magnitude of AC interference. The performance index of such a chip is shown in Table 3. It can be seen that the chip area and power consumption are very small, which is suitable for implanting the chip.
[0057] table 3
[0058] gate delay
PUM
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