Clock signal generation circuit, grid driving circuit, display panel and display device

Abstract

The invention relates to a clock signal generation circuit, a grid driving circuit, a display panel and a display device. The clock signal generation circuit comprises a selecting module, a high level signal input end, a low level signal input end, a first clock signal end, a second clock signal end and an output end, wherein the first clock signal end is used for inputting a first clock signal to the selecting module; the second clock signal end is used for inputting a second clock signal to the selecting module; the selecting module is used for gating or disconnecting the high level signal input end with the output end according to the first clock signal, and gating or disconnecting the low level signal input end with the output end according to the second clock signal; the selecting module is also used for gating the high level signal input end and the low level signal input end with the output end in turn and enabling the output end to output a target clock signal. The clock signal generation circuit is capable of reducing distortion of the target clock signal.

Description

technical field [0001] The present invention relates to the field of display technology, in particular to a clock signal generating circuit, a gate driving circuit, a display panel and a display device. Background technique [0002] A thin film transistor liquid crystal display (Thin Film Transistor Liquid Crystal Display, hereinafter referred to as TFT LCD) generally implements display in a progressive scanning manner. The progressive scanning is realized by the gate drive circuit and the source drive circuit; specifically, the gate drive circuit converts the clock signal through the shift register and sequentially loads the clock signal on multiple gate lines of the display panel, thereby driving multiple rows of pixels The thin film transistors are turned on sequentially, and the source drive circuit provides corresponding data signals to each pixel in the turned-on pixel row, so as to realize the display of each row of pixels and the row-by-row display of multiple rows o...

AI Technical Summary

Problems solved by technology

[0003] In the existing TFT LCD, the clock signal is connected to multiple rows of pixels, and its load is relatively large. This will cause the increase in the number of pixel rows scanned by the gate drive circuit when each frame is displayed, due to the resistance in the signal transmission line (there is resistance in the signal line) and capacitance (the shift register is equivalent to capacitance), the clock signal will gradually attenuate and be distorted; especially in TFT LCD with higher resolution, due to its large number of rows, in When scanning to several rows at the far end, the distortion of the clock signal may even lead to insufficient charging, which cannot drive the pixels of these rows to turn on

For example, if figure 1 As shown, when the gate drive circuit scans the nth row of pixels, the clock signal has been obviously distorted. The thin film transistors are turned on, so that the display of the row of pixels cannot

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