Vertical nanowire MOS transistor and method of forming the same

Abstract

Provided are a vertical nanowire MOS transistor and a forming method thereof. The vertical nanowire MOS transistor forming method comprises: providing a semiconductor substrate equipped with a well region therein; forming a first heavily doping region in the well region; forming a single crystal semiconductor layer on the surface of the semiconductor substrate; etching the single crystal semiconductor layer and a certain thickness of the first heavily doping region until the single crystal semiconductor layer forms a vertical nanowire, wherein the first heavily doping region is etched to form a first sub doping region and a second sub doping region; forming a dielectric layer on the top surface of the semiconductor substrate, the top surface of the well region, the top surface of the first heavily doping region, and the side surface of the vertical nanowire; forming a metallic gate layer to surround the dielectric layer on the side surface of the vertical nanowire; and performing heavily doping on the top of the vertical nanowire in order to form a second heavily doping region. The forming method simplifies process, reduces cost, and is suitable for large-scale production.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a vertical nanowire MOS transistor and a forming method thereof. Background technique [0002] With the increase of integrated circuit density, the performance of semiconductor products continues to improve, and the cost continues to decline, which benefits from the continuous shrinking of the size of MOS (Metal-Oxide-Semiconductor) transistor devices. However, when the device size of MOS transistors is reduced to the nanometer level, the short channel and subthreshold performance degrade rapidly. In order to suppress the performance degradation of MOS transistor devices and make integrated circuits still have good performance at the nanometer level, innovations can be made in terms of device structure. [0003] In the nanowire-based MOS transistor device, since the nanowire film in the channel region has a cylindrical structure, the corner effect is eliminated, which ...

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Problems solved by technology

[0005] However, in the existing methods of forming vertical nanowire MOS transistors, no matter based on bulk silicon substrate or SOI, there are problems of complex preparation process and high manufacturing cost, and the formed vertical nanowire transistors have low performance, vertical nanowire transistors Line MOS transistors and their formation methods are still a difficult problem to be solved in the industry

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