Semiconductor device and manufacturing method thereof

Abstract

Provided are a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate, an epitaxial layer, and a gate electrode structure. The epitaxial layer is disposed on the top of the substrate and comprises multiple first trenches and multiple second trenches which are arranged alternately in the first direction. The epitaxial layer between each pair of the first trench and the second trench which are adjacent comprises a first doped region and a second doped region which have different conductive types. An interface between the each first doped region and the corresponding second doped region forms a super junction structure. The epitaxial layer under the gate electrode structure comprises a channel extending in the second direction vertical to the first direction. Compared with a product in the prior art, the semiconductor device is increased in driving current gate-on sectional area, improved in driving current, and decreased in gate-on resistance.

Description

technical field [0001] The present invention relates to a semiconductor technology, in particular to a semiconductor device with a super junction structure and a manufacturing method thereof. Background technique [0002] The existing vertical diffused metal oxide semiconductor field effect transistor (VDMOSFET) mainly forms a P-N junction by an N-type epitaxy (Epitaxy) drift region (Drift region) and a P-type base (Base) doping region above it, and the semiconductor element The withstand voltage is mainly borne by the P-N junction. When increasing the operating voltage of a semiconductor device, it is necessary to reduce the dopant concentration and increase the thickness of the N-type epitaxial drift region. In contrast, the above method of increasing the withstand voltage of the P-N junction will also increase the on-resistance (Ron) of the device, and the on-resistance is also limited by the dopant concentration and thickness of the N-type epitaxial drift region. The d...

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Problems solved by technology

However, the pillar-type N-type doped region and pillar-type P-type doped region of this technology are limited by the depth that can be reached by ion implantation and subsequent thermal diffusion, so the cross-sectional area of ​​current conduction is also limited

To increase the total surface area of ​​the N-type doped region and the P-type doped region, the size of the element must be increased

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