A task-level out-of-order multiple-issue scheduler and its scheduling method
A multi-launch and scheduler technology, applied in multi-program devices, resource allocation, etc., can solve problems such as low efficiency of correlation acquisition, instruction-level scheduler can not meet the design requirements of task-level coarse-grained scheduler, etc., and achieve parallelism Execution efficiency, high computing resource utilization efficiency, and the effect of efficient dynamic scheduling
Active Publication Date: 2018-05-18
HEFEI UNIV OF TECH
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Problems solved by technology
The basic idea of the dynamic scheduler is the application of the Tomasulo algorithm, which is very mature in the traditional instruction-level scheduler, but the design of the traditional instruction-level scheduler can no longer meet the design requirements of the task-level coarse-grained scheduler
However, the existing design of task-level schedulers, such as the scalability of broadcast-based schedulers, has serious problems; and the dependency matrix-based scheduler requires the expression of dependencies as "producer-consumer" instructions, so Inefficient acquisition of task-task dependencies
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[0046] In this example, if figure 1 As shown, a task-level out-of-order multi-issue scheduler is arranged in a processor and is used to schedule M task instructions. The processor includes: an instruction fetch unit, a register state table and a processing unit array; the scheduler includes: Reserved station, selective wake-up unit and computing resource management unit; reserved station includes write address management unit, storage space and reserved station state table; selected wake-up unit includes age table, ready query unit and ready counter; computing resource management unit includes Calculation resource table, allocation unit and recycling unit;
[0047] Usually, a processor that supports dynamic scheduling includes a controller and a processing unit array. The controller includes an instruction fetching and decoding unit, a register renaming unit, a scheduler, a submission unit, physical registers, a register status table, etc.; The decoding unit obtains task inst...
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The invention discloses a task-level out-of-sequence multi-launch scheduler and its scheduling method, which is characterized in that the scheduler includes: a reservation station, a selective wake-up unit and a computing resource management unit; the reservation station includes a write address management unit, a storage space and reservation station state table; select wakeup unit includes age table, ready query unit and ready counter; computing resource management unit includes computing resource table, allocation unit and recovery unit. The invention can improve the throughput rate and resource utilization efficiency of the scheduler, thereby improving task command emission efficiency and system performance.
Description
technical field [0001] The invention relates to a task-level out-of-order multi-issue scheduler and a scheduling method thereof, belonging to the field of out-of-order multi-issue processors. Background technique [0002] With the development of integrated circuit technology, the requirements for processor performance are getting higher and higher. The improvement of processor performance, on the one hand, depends on the development of integrated circuit technology; on the other hand, it also depends on the progress of processor design technology. Theme of. For a large part of the past, many efforts have been made to mine instruction-level parallelism. Technologies such as super-pipeline structure, superscalar structure, instruction out-of-order multiple issue, and very long instruction word VLIW have been applied in many processors. With the development of multi-core processors, the current multi-core technology has become the main technical method to improve processor pe...
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IPC IPC(8): G06F9/50
Inventor 张多利张扬宋宇鲲杜高明
Owner HEFEI UNIV OF TECH