Semiconductor device with features to prevent reverse engineering

Abstract

The ROM circuit includes: a first N-channel transistor having an output and device geometry and device characteristics suitable for biasing the output at a predetermined level when the P-channel circuit is connected to the first N-channel transistor; a pass transistor , connected between the output and the data bus, the pass transistor connected to a word line adapted to turn on the pass transistor when the word line is asserted; and a P-channel circuit connected to the data bus and adapted to A leakage current is provided to charge the gate of the first N-channel transistor when the pass transistor is turned on.

Description

[0001] This application claims priority to U.S. Patent Application Serial No. 13 / 739,463, filed November 2013, which is a continuation-in-part of U.S. Patent Application Serial No. 13 / 663,921, filed October 30, 2012, which was filed July 29, 2011 13 / 194,452, which claims the benefit of US Provisional Application Serial No. 61 / 494,172, filed July 2011, which is hereby incorporated by reference in its entirety. Background technique [0002] It is hoped to design electronic chips that are difficult to reverse engineer in order to protect circuit designs. Known reverse engineering techniques include methods that disassemble layers of a chip to expose logic devices. [0003] Semiconductor teardown techniques typically involve imaging a device layer, removing that layer, imaging the next layer, removing that layer, and so on until a complete representation of the semiconductor device is achieved. Imaging of the layers is usually accomplished with an optical or electron microscope. ...

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