Sampling time error calibrating device and method of multi-channel parallel analog-to-digital conversion system

A technology of sampling time and analog-to-digital conversion, applied in the direction of analog/digital conversion calibration/testing, analog-to-digital converter, etc., can solve the problems of inability to correct sampling time error and difficulty in correcting sampling time error, so as to facilitate hardware implementation and calibration Sampling time error, effect of reducing complexity

Active Publication Date: 2015-11-04
DATANG MICROELECTRONICS TECH CO LTD +1
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Problems solved by technology

[0004] For a multi-channel parallel ADC system, the sampling time error is related to the system input signal frequency. When the system input signal frequency is greater than the Nyquist frequency of a single ADC, each channel does not satisfy the Nyquist theo

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  • Sampling time error calibrating device and method of multi-channel parallel analog-to-digital conversion system
  • Sampling time error calibrating device and method of multi-channel parallel analog-to-digital conversion system
  • Sampling time error calibrating device and method of multi-channel parallel analog-to-digital conversion system

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[0023] In order to make the objectives, technical solutions and advantages of the present invention clearer, the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be noted that the embodiments in the application and the features in the embodiments can be combined with each other arbitrarily if there is no conflict.

[0024] The steps shown in the flowchart of the drawings can be executed in a computer system such as a set of computer-executable instructions. Also, although a logical sequence is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than here.

[0025] figure 1 It is a schematic diagram of a calibration device for sampling time error of a multi-channel parallel analog-to-digital conversion system in an embodiment of the present invention. Such as figure 1 As shown, the device includes: a clock generation circuit 1, a time alternating anal...

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Abstract

The invention discloses a sampling time error calibrating device and method of a multi-channel parallel analog-to-digital conversion system. The method comprises that analog input signals are input at the input end of a TIADC system; the output end of the TIADC system is connected with the input end of a sampling time error estimation circuit via a switch circuit; the output end of the TIADC system is also connected with the input end of a multiplexer, and sends sampling time error values to a sampling time error compensating circuit; and the output end of the multiplexer and the output end of the sampling time error estimating circuit are connected to the input end of the sampling time error compensating circuit, and output signals at the output end of the sampling time error compensating circuit serve as calibrated output signals. According to the sampling time error calibrating device and method, sampling time errors of the TIADC system are calibrated, the problem of aliasing is solved, the operation speed of the calibration circuit is increased, and convenience is provided for hardware realization.

Description

technical field [0001] The invention relates to the technical field of high-speed and high-precision analog-to-digital conversion, in particular to a device and method for calibrating sampling time errors of a multi-channel parallel analog-to-digital conversion system. Background technique [0002] With the development of digital signal processing technology, digital circuits have higher and higher requirements on the sampling rate of analog-to-digital converters. The most important performance parameters of an analog-to-digital converter (ADC, Analog-to-digital converter) are conversion accuracy and conversion speed. However, the speed and precision of the ADC are mutually restricted. With the increase of the conversion speed of the ADC, its precision tends to decline. Due to the limitation of the development level of the current ADC chip, it is difficult for a single ADC to have high speed and high precision at the same time. [0003] In order to achieve a higher sampling...

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Application Information

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IPC IPC(8): H03M1/10H03M1/12
Inventor 齐佩佩高洪福
Owner DATANG MICROELECTRONICS TECH CO LTD
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