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Sn-based interconnection material for three-dimension packaging chip stacking

A technology of interconnection materials and chip stacking, applied in the direction of electrical components, nanotechnology, electrical solid devices, etc., can solve the problems of lack of reports, three-dimensional packaging structure is prone to early failure, etc., and achieve the effect of high service life

Inactive Publication Date: 2015-11-11
XUZHOU NORMAL UNIVERSITY
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, the three-dimensional packaging structure is prone to early failure due to the two shortcomings above the intermetallic compound solder joints.
Therefore, the development of new 3D packaging interconnection materials is the key to improving the reliability of interconnection solder joints in 3D packaging structures, but there is currently a lack of relevant reports in the international community on this aspect of research.

Method used

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  • Sn-based interconnection material for three-dimension packaging chip stacking

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Experimental program
Comparison scheme
Effect test

Embodiment 1

[0016] The composition of the Sn-based interconnection material used for stacking of three-dimensional packaged chips is: nano-graphene 5%, SiC nanowire 6%, and the balance is Sn.

[0017] The service life of the "reinforced concrete" structural solder joints formed after bonding (260°C, 1MPa) is about 3750 thermal cycles (considering the experimental error), and the paste interconnection material has excellent solderability.

Embodiment 2

[0019] The composition of the Sn-based interconnection material used for three-dimensional packaging chip stacking is: nano-graphene 8%, SiC nanowire 10%, and the balance is Sn.

[0020] The service life of the "reinforced concrete" structural solder joints formed after bonding (255°C, 10MPa) is about 4950 thermal cycles (considering the experimental error), and the paste interconnection material has excellent solderability.

Embodiment 3

[0022] The composition of the Sn-based interconnection material used for stacking of three-dimensional packaged chips is: nano-graphene 8%, SiC nanowire 9%, and the balance is Sn.

[0023] The "reinforced concrete" structure solder joint formed after bonding (235°C, 5MPa) has a service life of about 4700 thermal cycles (considering the experimental error), and the paste interconnection material has excellent solderability

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Abstract

The invention discloses a Sn-based interconnection material for three-dimension packaging chip stacking, and belongs to the field of chip interconnection materials. The interconnection material comprises 5-8% of graphene nanoparticles and 6-10% of SiC nanowires, with the balance being Sn. Commercially available Sn powder, mixed rosin resin, thixotropic agent, stabilizer, active assistant agent and activator are fully mixed; then, graphene nanoparticles are added; and finally, SiC nanowires are added, and the materials are fully mixed to prepare a paste-like interconnection material containing graphene nanoparticles and SiC nanowires. Bumps are prepared on the surfaces of chips by a printing method, vertical chip stacking and interconnection is realized at certain pressure (1-10MPa) and temperature (235-260 DEG C), and 'reinforced concrete' solder joints are formed. The interconnection material of the invention has high reliability, and can be used for three-dimension packaging chip stacking.

Description

technical field [0001] The invention relates to a Sn-based interconnection material used for three-dimensional package chip stacking, and belongs to the field of chip interconnection materials. The interconnection material is mainly used in the field of three-dimensional packaging with high reliability requirements, and is a new type of interconnection material with high performance. Background technique [0002] With the rapid development of portable electronic products, electronic devices are gradually developing in the direction of low power, light weight and small package. When the two-dimensional assembly density has reached the theoretical maximum, the three-dimensional packaging chip stacking technology has become a hot spot pursued by the international community. Three-dimensional packaging, that is, stacking chips layer by layer in three-dimensional space, can achieve the dual functions of reducing chip size and improving data transmission speed. [0003] Since th...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/532H01L21/768H01L23/488H01L21/60B82Y40/00
Inventor 张亮郭永环孙磊
Owner XUZHOU NORMAL UNIVERSITY
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