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Integrated circuit design method and integrated circuit

A technology of integrated circuits and design methods, applied in circuits, calculations, electrical components, etc., can solve problems that are not conducive to cost saving, unfavorable chip miniaturization, large chip area, etc., and achieve the goal of increasing density, saving costs, and increasing device density Effect

Active Publication Date: 2018-03-16
SEMICON MFG INT (BEIJING) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The existence of the distance L will lead to a relatively low device density in the layout, and accordingly, the device density in the manufactured integrated circuit (chip) will also be relatively low (that is, resulting in a relatively large chip area)
Obviously, this is not conducive to the miniaturization of the chip, and it is not conducive to saving costs

Method used

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  • Integrated circuit design method and integrated circuit
  • Integrated circuit design method and integrated circuit
  • Integrated circuit design method and integrated circuit

Examples

Experimental program
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Embodiment 1

[0033] This embodiment relates to the technical field of integrated circuits, and in particular, this embodiment relates to a method for designing an integrated circuit, which is used to reduce the area of ​​a layout (layout), thereby reducing the area of ​​a chip.

[0034] In the integrated circuit to be designed by the integrated circuit design method of this embodiment, it includes such as figure 2 A first transistor 11 and a second transistor 12 are shown. Wherein, the first transistor 11 includes a fin structure 101, a gate 102, an active region 103, and an edge gate (edge ​​gate) 1021, and the second transistor 12 includes a fin structure 201, a gate 202, an active region 203, an edge gate Gate (edge ​​gate) 2021. The positions of two adjacent edge gates 1021 and 2021 of the first transistor 11 and the second transistor 12 overlap, and a middle gate (middle gate) 1022 is formed at the overlapping position of the edge gates. Wherein, the intermediate gate 1022 and the ...

Embodiment 2

[0058] This embodiment provides an integrated circuit, which is manufactured according to the layout designed by the design method described in the first embodiment.

[0059] in, Figure 4 A layout of the integrated circuit of this embodiment is shown. like Figure 4 As shown, the integrated circuit of this embodiment includes: a first transistor 11 and a second transistor 12 adjacent to each other, and a second transistor including an intermediate gate 1022 disposed at the junction of the first transistor 11 and the second transistor 12 Three transistors 13 (also referred to as intermediate gate transistors), wherein the intermediate gate 1022 is connected to a predetermined voltage Voff so that the third transistor 13 is in an off state.

[0060] Wherein, the purpose of turning off the third transistor 13 by connecting the predetermined voltage Voff is to isolate the first transistor 11 and the second transistor 12 .

[0061] Exemplarily, when the intermediate gate transi...

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Abstract

The invention provides an integrated circuit design method and the integrated circuit, which relate to the technical field of integrated circuits. The design method includes: step A: changing the positions of the first transistor and the second transistor that are adjacent to each other at a certain distance in the integrated circuit, so that the two adjacent edge gates of the first transistor and the second transistor are and forming a third transistor including an intermediate gate at the overlapping position of the edge gates; step B: turning off the third transistor by connecting the intermediate gate to a predetermined voltage to isolate the first transistor with the second transistor. The design method can increase the device density of the integrated circuit and reduce the cost. The integrated circuit of the present invention is manufactured according to the layout designed by the design method, so it has the advantages of high device density and low cost.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to an integrated circuit design method and the integrated circuit. Background technique [0002] In the field of integrated circuit technology, reducing chip area has always been a goal pursued by the industry. For advanced technologies, especially for 32nm and below process nodes, reducing chip design area is a key factor for cost savings. [0003] In integrated circuit design, if the sources or drains of two transistors are not connected together, the two transistors should be separated in space (that is, a certain distance should be kept between them), such as figure 1 shown. exist figure 1 In the layout of the shown integrated circuit, it includes a first transistor 1 and a second transistor 2. The first transistor 1 includes a fin structure 1001, a gate 1002, an active region 1003, an edge gate (edge ​​gate) 10021, and a second transistor 1002. The transistor 2 ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/02G06F17/50
CPCH01L21/823431H01L21/823437H01L21/823475H01L21/823481H01L27/0207H01L27/088H01L27/0886H01L22/14H01L22/22
Inventor 沈忆华余云初钟浩
Owner SEMICON MFG INT (BEIJING) CORP