Low Power 3-Tap Decision Feedback Equalizer for High-Speed ​​Serial Interface Receiver

Abstract

The invention belongs to the technical field of data transmission, and in particular relates to a low-power consumption 3-tap decision feedback equalizer for a high-speed serial interface receiving end, which includes two data paths with the same structure, namely an odd data path and an even data path; each A data path includes a gain stage, an offset cancellation unit, a dynamic combining summer, a dynamic latching summer, a buffer, a dynamic feedback stage, and a splitter; The gain stages and offset elimination units in the odd and even data paths form the equalized front end; the dynamic latch summers, dynamic feedback stages, and buffers in the odd and even data paths form the first tap loop; the odd and even data paths The second and third tap loops are composed of a dynamic combiner, summer, and splitter; the summing unit of the entire 3-tap module is clock-controlled. The invention has the characteristics of low power consumption, high working speed and strong balancing ability.

Description

technical field [0001] The invention belongs to the technical field of data transmission, and in particular relates to a low-power consumption 3-tap decision feedback equalizer used for a high-speed serial interface receiving end. Background technique [0002] In recent years, the data rate transmitted by high-speed serial port transceivers has been rising continuously. At present, the data rate of a single channel has reached more than 40Gbps. Under such a high data rate, the channel will seriously attenuate the signal. At this time, the design of the receiver is faced with Serious ISI problem. Commonly used equalizers mainly include Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalizer (DFE). The decision feedback equalizer is widely used in the design of the receiving end of the high-speed serial interface. The decision feedback equalizer is placed at the front end of the receiver to compensate the serial data from the channel in time domain and elimina...

AI Technical Summary

Problems solved by technology

Although this speculative structural design can relax the timing requirements for the first tap critical path, it is not conducive to the design of the second and subsequent tap loops. The reason is that the data selector will introduce a large amount of load and add additional time delays. , on the other hand, the number of data selectors will increase exponentially with the number of taps

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