Structure and manufacturing method of fan-out package

Abstract

The invention provides a structure and manufacturing method of a fan-out package. The structure includes a chip with electrodes, the active surface of the chip faces upward, and the periphery of the chip is filled with a first insulating resin layer. The top of the first insulating resin layer is larger than the upper surface of the chip. High; the top of the chip and the first insulating resin layer is covered with a second insulating resin layer, and the surface of the second insulating resin layer has a rewiring layer connected to the electrode of the chip through the opening of the second insulating resin layer; the second insulating resin layer The layer and the redistribution layer are covered with a third insulating resin layer, the third insulating resin layer has an opening, exposing the pad of the redistribution layer, and the pad of the redistribution layer is connected with a conductive column, and the conductive column passes through the redistribution layer It is electrically connected with the electrode on the active surface of the chip; there is a protective layer on the bottom of the chip and the first insulating resin layer. The package structure of the invention does not have a carrier sheet, which is beneficial to reduce the package thickness, and also expands the application range of the technology; and no copper pillars are made in the chip, which is beneficial to the reduction of cost.

Description

technical field [0001] The invention relates to a fan-out package (FOWLP) structure and a manufacturing method, belonging to the technical field of integrated circuit chip packaging. Background technique [0002] With the trend of multi-function and miniaturization of electronic products, high-density microelectronic assembly technology has gradually become the mainstream in the new generation of electronic products. In order to cope with the development of a new generation of electronic products, especially the development of smart phones, PDAs, ultrabooks and other products, the size of chips is developing in the direction of higher density, faster speed, smaller size, and lower cost. The emergence of Fan-Out Wafer Level Package (FOWLP) technology has satisfied the characteristics of thinner chip products and saving materials (packaging substrates), but how to reduce the cost of Fan-Out Wafer Level Package products has become The direction of research is needed. [0003]...

AI Technical Summary

Problems solved by technology

[0009] The disadvantage of this technology is that the first insulating resin layer is coated in the third step of the process. Since the thickness of the chip is usually more than 50 microns, the thickness of the coated insulating resin is not easy to control, which is not conducive to the production of fine lines.

[0011] The disadvantage of this technology is that it needs a substrate as a carrier, which increases the complexity of the process and is not conducive to the reduction of the overall thickness of the chip.

Although this technology avoids the use of the second carrier board, the production of copper pillars, the grinding and polishing of the plastic sealing layer, and the control of the outcropping of copper pillars make this technology very expensive

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