Semiconductor test structure

Abstract

A semiconductor test structure is disclosed. A second test metal layer surrounds several perforating silicon through hole structures. One end of each perforating silicon through hole is connected to a first test metal layer. The first test metal layers and the second test metal layer are located on a same surface of a semiconductor substrate so as to connect the first test metal layers into one integral body. Through connecting the first test metal layers of the perforating silicon through hole structures into one integral body, distortion and deformation of the first test metal layer at one perforating silicon through hole structure can cause the distortion and deformation of the first test metal layers at the perforating silicon through hole structures so that a deformation quantity of the above distortion and deformation is amplified, which easily causes that conductive materials in the perforating silicon through holes can not be isolated by an insulating layer and are diffused into the semiconductor substrate. At this time, a test voltage is exerted on two ends of the perforating silicon through hole structures so that a current between the first test metal layers and the second test metal layer can be easily detected; the above current is a leakage current so that the perforating silicon through hole structure with unreliable performance can be easily detected through using the above test structure.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a semiconductor testing structure. Background technique [0002] With the continuous development of semiconductor technology, the feature size of semiconductor devices has become very small, so it is becoming more and more difficult to increase the number of semiconductor devices in a two-dimensional packaging structure. In view of the above problems, a three-dimensional packaging technology is currently proposed to improve the integration level of chips. Current three-dimensional packaging includes gold wire bonding-based chip stacking (DieStacking), packaging stacking (PackingStacking), and through-silicon via (ThroughSiliconVia, TSV)-based three-dimensional stacking. Among them, the three-dimensional stacking using through-silicon vias has the following three advantages: 1) high-density integration; 2) greatly shortening the length of electrical interconnections, which...

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Problems solved by technology

However, in the chip manufacturing process, multiple annealing steps are involved, which causes the TSV structure and the semiconductor substrate to withstand a certain temperature, and the conductive material filled in the TSV, such as copper, is not compatible with the material of the semiconductor substrate. , for example, the thermal expansion coefficient of silicon has a large difference, for example, the thermal expansion coefficient of copper is 16ppm / ℃, and the thermal expansion coefficient of silicon is 3ppm / ℃, which results in a large stress difference between the two. When the above stress difference is transferred to the insulating layer, It is easy to cause distortion and deformation of the insulating layer, deterioration of electrical insulation performance, or even rupture, and the conductive material will diffuse into the semiconductor substrate or interlayer dielectric layer (ILD), correspondingly causing leakage current or semiconductor leakage between adjacent TSV structures. The reliability between the first metal layer patterns (M1) on the surface of the substrate deteriorates, which all lead to unreliable performance of the chip, which in turn leads to unreliable performance of the packaging structure

In addition, because TSVs generally have a deep depth, reaching hundreds of nanometers or even thousands of nanometers, and the aspect ratio is large, when the insulating layer is formed on the sidewall, the thickness cannot be guaranteed to be uniform, or even the sidewall is completely covered. , which further leads to poor performance and easy cracking of the insulating layer when it is twisted and deformed, which in turn causes unreliable performance of the chip packaging structure in the working process

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