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Semiconductor Device And Method Of Forming The Same

A semiconductor and complementary technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems such as difficult control of leakage current, inability to apply flexible substrates, loss of practicability, etc.

Inactive Publication Date: 2015-12-30
IND TECH RES INST
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, low-temperature polysilicon components require at least six photolithography and etching processes (Photolithography and Etch Process; PEP), plus ion implantation, annealing, hydrogenation and other manufacturing processes, making the manufacturing process steps very complicated.
In addition, the value of the threshold voltage (Vt) of the formed CMOS and the leakage current at the operating voltage of 0V are not easy to control, making the CMOS characteristics poor and impractical
On the other hand, high-temperature polysilicon components are also complicated in the manufacturing process, and the high temperature prevents this technology from being applied to flexible substrates.

Method used

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  • Semiconductor Device And Method Of Forming The Same
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  • Semiconductor Device And Method Of Forming The Same

Examples

Experimental program
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no. 1 example

[0092] Figure 1A to Figure 1E It is a schematic cross-sectional view of the manufacturing method of the semiconductor device according to the first embodiment of the present invention.

[0093] Please refer to Figure 1A , providing a substrate 100. The substrate 100 can be a rigid substrate or a flexible substrate. A rigid substrate is, for example, a glass substrate or a silicon substrate. Flexible substrates are, for example, metal sheets or plastic substrates. The substrate 100 has a first region 100a and a second region 100b. In one embodiment, the first region 100 a is, for example, a P-type device region, and the second region 100 b is, for example, an N-type device region.

[0094] Next, please refer to Figure 1A and Figure 1B , forming a semiconductor layer 103 on the substrate 100 in the first region 100a. The material of the semiconductor layer 103 of the present invention includes low temperature polysilicon (LTPS), and its manufacturing process temperatu...

no. 2 example

[0106] Figure 2A to Figure 2D It is a schematic cross-sectional view of a manufacturing method of a semiconductor device according to a second embodiment of the present invention. The second embodiment is similar to the first embodiment, the differences will be described below, and the similarities will not be repeated.

[0107] First, please refer to Figure 2A , providing a substrate 200 . The substrate 200 has a first region 200a and a second region 200b. In one embodiment, the first region 100 a is, for example, a P-type device region, and the second region 100 b is, for example, an N-type device region. Next, a semiconductor layer 203 is formed on the substrate 200 in the first region 200a. Then, a dielectric layer 204 is formed on the substrate 200 in the first region 200 a and the second region 200 b, and the dielectric layer 204 covers the semiconductor layer 203 . Afterwards, a gate 206 and a gate 208 are respectively formed on the dielectric layer 204 in the fi...

no. 3 example

[0114] 3A to Figure 3B It is a schematic cross-sectional view of a manufacturing method of a semiconductor device according to a third embodiment of the present invention. The third embodiment is similar to the second embodiment, and the differences will be described below, and the similarities will not be repeated.

[0115] First, provide Figure 2B intermediate structure. Then, please refer to Figure 3A , performing a patterning step to form two openings 220 , two openings 222 and one opening 223 in the dielectric layer 204 , the dielectric layer 214 and the dielectric layer 218 . The opening 220 penetrates through the dielectric layer 204 , the dielectric layer 214 and the dielectric layer 218 and respectively exposes the doped region 210 of the semiconductor layer 203 . The opening 222 penetrates through the dielectric layer 218 and exposes a portion of the upper surface of the semiconductor layer 216 . The opening 223 penetrates through the dielectric layer 214 and...

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Abstract

A semiconductor device is provided. A first semiconductor layer is disposed on a substrate and has a channel region and two doped regions beside the channel region. A first dielectric layer is disposed on the substrate and covers the first semiconductor layer. A gate is disposed on the first dielectric layer and corresponds to the channel region of the first semiconductor layer. A second dielectric layer is disposed on the first dielectric layer and covers the gate. A second semiconductor layer is disposed on the second dielectric layer and corresponds to the gate. The boundary of the second semiconductor layer does not exceed that of the gate. At least one first conductive plug penetrates through the first and second dielectric layers and contacts one doped region of the first semiconductor layer. At least one contact contacts the second semiconductor layer. A method of forming a semiconductor device is also provided.

Description

[0001] The present invention is a divisional application of the invention patent application with the application number 201210059206.2 and the invention name "semiconductor element and its manufacturing method" filed on March 8, 2012. technical field [0002] The present invention relates to a semiconductor device and its manufacturing method, and in particular to a semiconductor device including low temperature polysilicon (LTPS) and metal oxide semiconductor and its manufacturing method. Background technique [0003] Complementary metal-oxide-semiconductor (CMOS) devices have the advantage of only consuming power when the transistor needs to be switched on and off, so it saves power and generates less heat. In addition, many logic circuits also need to be easily achieved through the characteristics of CMOS. [0004] Generally speaking, the manufacturing process temperature of low temperature polysilicon components is about 600°C. However, low-temperature polysilicon devi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/12H01L21/77
CPCH01L27/1225H01L27/1251
Inventor 颜精一林政伟许智杰何金原
Owner IND TECH RES INST