Method for forming self-aligned split-gate flash memory

Abstract

A method for forming a self-aligned split-gate flash memory, comprising: sequentially forming a thermal oxide layer, a floating gate layer, and a hard mask layer on the surface of a substrate, the hard mask layer having an opening exposing the thermal oxide layer; An ONO layer is formed on the surface of the mask layer and in the opening; a composite layer is formed on the surface of the ONO layer; the composite layer and the ONO layer are etched by an etching process until the surface of the hard mask layer and the surface of the floating gate layer are exposed , forming sidewalls on both sides of the first opening, and the sidewalls are located on the surface of the ONO layer at the bottom of the first opening; using the sidewalls as a mask to etch the floating gate layer and the thermal oxide layer; The first spacer on the top surface of the wall and the second sidewall on the side of the sidewall, the floating gate layer and the thermal oxide layer; fill the first opening with the polysilicon layer, and planarize the polysilicon layer until the exposed On the surface of the hard mask layer, a structure in which the control gate and the source line are integrated is formed. Embodiments of the present invention do not need additional ports.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a self-aligned split-gate flash memory. Background technique [0002] Flash memory is an important non-volatile semiconductor memory. Flash memory has the advantages of high storage density, low cost, and good reliability, and is widely used in industrial control, mobile phones, and communications. The basic principle of flash memory is to change the switching state of memory cells by injecting and erasing charges (electrons) on the floating gate of flash memory, so as to achieve the purpose of storing data. [0003] From the basic classification of architecture, flash memory is divided into two types: NAND and NOR. NAND is more suitable for mass data storage, requiring high-density storage units and low cost; NOR is more suitable for program storage, requiring random readability, high-speed reading, and directly exchanging information with microp...

AI Technical Summary

Problems solved by technology

[0005] Like the mainstream logic CMOS process, continuous reduction of cell area and cost reduction are also the main direction of flash memory development. From the published data, with the reduction of cell area, it is often necessary to add additional ports, such as control gates, erase Gate, etc., which brings additional complexity to the design, requires additional decoding devices, and increases the area of ​​the peripheral area, which is especially unfavorable for the application of low-to-medium density, and weakens the cost reduction effect brought about by the reduction of unit size.

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