DDR (Double Data Rate) controller and controlling method based on FPGA (Field Programmable Gate Array)

Abstract

This invention discloses a DDR controller and controlling method based on FPGA. The controller comprises a state machine, a configuration control unit, an activation control unit, a read-write control unit, a precharge control unit, a refresh control unit and a port control unit; the state machine is used for completing time sequence control function of the DDR controller, realizing access to a DDR memory, and switching between corresponding states according to access requirements; the configuration control unit is used for configuring when the DDR memory is powered on; the activation control unit is used for activating data arrays of the DDR memory; the read-write control unit is used for synchronously processing external access, giving a read-write mark, and judging whether the read-write mark is burst read-write or single-period read-write; the precharge control unit is used for completing invalid operation to activated row unit; the refresh control unit is used for charging the data arrays; and the port control unit is used for latching ports of a data bus, an address bus and a control bus. The method provided by the invention is beneficial to solve the problem for controlling the DDR memory.

Description

technical field [0001] The invention relates to an FPGA-based DDR controller and an FPGA-based DDR control method. Background technique [0002] DDR memory has the characteristics of miniaturization and large capacity, and is widely used in CPU systems, data acquisition systems and other fields as data memory. In the field of data acquisition systems, it is mainly used as a data cache. How to realize the control of DDR memory so that it can meet the requirements of data cache, usually use the FPGA core generator to realize the control of DDR memory and complete the reading, writing, refreshing, and processing of DDR memory. Pre-charging, power-on configuration and other operations. As the manufacturer's own dedicated IP core, the FPGA core will charge users and increase user costs. On the other hand, it is not flexible enough to use and can only be used as a general data cache control interface. It is difficult to meet the requirements for special use. The pins of the IP c...

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Problems solved by technology

As the manufacturer's own dedicated IP core, the FPGA core will charge users fees and increase user costs. On the other hand, it is not flexible enough to use and can only be used as a general data cache control interface. It is difficult to meet the requirements for special applications. The pins of the IP core FPGA are fixed and cannot be flexibly configured, which puts forward high requirements for the layout and wiring of the printed board

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