Formation method for fin type field-effect transistor

A fin-type field effect transistor and fin technology are applied in the direction of electrical components, semiconductor/solid-state device manufacturing, circuits, etc., which can solve the problem that the electrical performance of the fin-type field effect transistor needs to be improved, and achieve improved electrical performance and reliability. The effect of avoiding etching and maintaining integrity

Active Publication Date: 2016-02-17
SEMICON MFG SOUTH CHINA CORP
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  • Application Information

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Problems solved by technology

[0005] However, the electrical performance of the fin field effect transistor formed by the prior art needs to be improved

Method used

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  • Formation method for fin type field-effect transistor
  • Formation method for fin type field-effect transistor
  • Formation method for fin type field-effect transistor

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Embodiment Construction

[0034] It can be seen from the background art that the electrical performance of the fin field effect transistor formed in the prior art needs to be improved.

[0035] After research, it is found that in the prior art, when the source region and the drain region of the FinFET are used, the method of ion implantation is usually used to dope the fin of the FinFET; since the fin is a three-dimensional structure, the ion implantation When the angle is different, the concentration and implantation depth of ion implantation in the source region and the drain region will be different, resulting in the problem of non-conformal doping. The doping concentration of each region of the fin is different, for example, the top region of the fin The doping concentration of the doping concentration is higher than that of the sidewall region of the fin; the non-conformal doping problem is an important reason for the poor electrical performance of the FinFET.

[0036] Moreover, the ion implantati...

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Abstract

A formation method for a fin type field-effect transistor is disclosed. The formation method comprises the steps of providing a substrate, wherein a plurality of separated fin parts are formed on the surface of the substrate; forming a separating layer on the surfaces of the side walls and the top parts of the fin parts, wherein the etching speed on the separating layer and the etching speed on the fin parts in an etching process are different; forming an impurity layer on the surface of the separating layer, wherein the impurity layer has atoms with the same material as the fin parts ; the impurity layer is further provided with N type ions or P type ions; performing annealing treatment on the substrate to enable the N type ions or the P type ions in the impurity layer to be diffused into the fin parts through the separating layer to form a doping region in the internal of the fin parts; the impurity layer is converted into an intrinsic layer; taking the separating layer as the etching stop layer and etching off the intrinsic layer; and etching off the separating layer until the top parts and the side wall surfaces of the fin parts are exposed. The concentration uniformity of the formed doping region is improved, the amorphization problem on the fin parts caused by the ion implantation technology is avoided, the completeness of the sizes of the fin parts is kept, and the electrical property of the fin type field-effect transistor is optimized.

Description

technical field [0001] The invention relates to the technology in the field of semiconductor manufacturing, in particular to a method for forming a fin field effect transistor. Background technique [0002] With the continuous development of semiconductor process technology, the development trend of semiconductor process nodes following Moore's Law continues to decrease. In order to adapt to the reduction of process nodes, the channel length of MOSFET field effect transistors has to be continuously shortened. The shortening of the channel length has the advantages of increasing the die density of the chip and increasing the switching speed of the MOSFET field effect tube. [0003] However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control ability of the gate to the channel becomes worse, and the gate voltage pinches off (pinchoff) the channel. The difficulty is also increasin...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336H01L29/78
CPCH01L21/823821
Inventor 何永根
Owner SEMICON MFG SOUTH CHINA CORP
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