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A racetrack memory chip with temperature control based on quota and its control method

A storage chip and temperature control technology, which is applied in the field of track storage, can solve the problems of not exceeding the specified index, changing the electrical parameters of track storage, and burning storage materials, etc.

Active Publication Date: 2018-02-13
PEKING UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, both calculations and experiments show that the movement generates a lot of heat, which leads to changes in the temperature of the memory chip
A sharp rise in temperature will lead to changes in the electrical parameters of the track storage, drift in the moving speed of the magnetic domain wall, a decrease in the stability of the storage material, and even burnout of the storage material in severe cases
At present, none of the existing technologies can guarantee that the temperature of the track storage will not exceed the specified index during normal operation, and then there is no technology that can control its mobile density

Method used

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  • A racetrack memory chip with temperature control based on quota and its control method
  • A racetrack memory chip with temperature control based on quota and its control method
  • A racetrack memory chip with temperature control based on quota and its control method

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Embodiment Construction

[0026] The present invention will be further described through the embodiments below in conjunction with the accompanying drawings.

[0027] Such as figure 1 As shown, the track memory chip based on the quota control temperature of this embodiment includes: a substrate 1, a track memory bar 2, a filling layer 3 and a heat dissipation device 4; wherein, a plurality of parallel nanowires are grown on the substrate 1 As a track storage bar 2; a filling layer 3 is formed in the gap and above the nanowire; and a heat dissipation device 4 is arranged on silicon dioxide. Silicon dioxide is formed on the substrate 1 using single crystal silicon, followed by packaging environment substrate 01 and PCB board 02; nanowire 2 is made of Co 20 Fe 60 B 20 The nanowire filling layer 3 is made of amorphous silicon dioxide; between the filling layer 3 and the cooling device 4 is heat dissipation silica gel.

[0028] The track memory chip is a physical concept, and the track memory is its log...

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Abstract

The invention discloses a quota control temperature based racetrack memory chip and a control method therefor. The racetrack memory chip comprises a substrate, racetrack memory strips, a filling layer and a heat dissipation apparatus. A mobile quota is set in a program running interval, so that hot spot dispersion is performed in time; and moreover, a data block is stored in the non-adjacent racetrack memory strips, so that hot spot dispersion is performed in space. The invention provides a control method for a temperature rise of a racetrack memory due to mobile operation. The method comprehensively considers hot spot diffusion in time and space, so that the temperature rise of the chip can be reduced as far as possible; and due to analog display, the performance loss caused by the method is only 5% averagely.

Description

technical field [0001] The invention relates to race track storage technology, in particular to a race track memory chip and a control method thereof based on quota-based temperature control. Background technique [0002] Racetrack memory, also known as domain wall memory, is a memory that stores data based on the magnetic domain wall movement characteristics of spin magnetic materials. Due to its ultra-high storage density and access speed, track storage is gradually becoming a research hotspot in the academic and industry circles. Raceway storage utilizes large numbers of magnetic domains stored on strips of magnetic material to store data. However, in order to support high-density storage, track storage introduces a new operation: shift. A Racetrack memory Stripe (RS) is divided into multiple domains of equal length. The arrangement of domains is called a domain sequence, and some access terminals are evenly distributed, and each access terminal is responsible for acces...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/02G11B33/14
CPCG06F12/0246G06F2212/7201G06F2212/7209G11B33/1406
Inventor 孙广宇张超
Owner PEKING UNIV
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