30 results about "Racetrack memory" patented technology

Embodiments are directed to injecting domain walls in a magnetic racetrack memory. In some embodiments, a racetrack comprising a nanowire is coupled with a gate in order to manipulate an anisotropy associated with the nanowire. The racetrack and gate is coupled with a pinning layer configured to establish a magnetization direction in the nanowire.

A shift register is provided, the shift register comprising at least one track including a storage region. The storage region comprises a plurality of magnetic domains for storing data. A given first one of the plurality of magnetic domains is adjacent to a given second one of the plurality of magnetic domains. The given first one of the plurality of magnetic domains and the given second one of the plurality of magnetic domains are arranged in a linear configuration. Further, the given first one of the plurality of magnetic domains and the given second one of the plurality of magnetic domains are separated from one another by at least one layer of non-magnetic material. The at least one layer of non-magnetic material preventing a propagation of a nucleated wall from traveling between the given first one of the plurality of magnetic domains and the given second one of the plurality of magnetic domains. The shift register is configured such that an electric current applied to the track is operative to shift data stored within at least one of the plurality of magnetic domains of the storage region, along the track, in a direction of the electric current. The data stored within the at least one of the plurality of magnetic domains is shifted as a function of the direction of the electric current.

The invention discloses a track memory based on magnetic skyrmions, belonging to the technical field of magnetic devices. Including antiferromagnetically coupled double-track magnetic nanoribbons, the magnetic nanoribbons are divided into information writing part, information storage part and information reading part along the track direction, and the binary number 0 or 1. Magnetic skyrmions move from the information writing part to the information reading part along the track direction of the double-track magnetic nanobelt; the magnetic skyrmions periodically move in one of the tracks of the double-track magnetic nanobelt where the information writing part is located Generated, the generated magnetic skyrmions determine whether to change the polarity according to the written data, and then determine whether to move to another track of the double-track magnetic nanoribbon; the information storage part is divided into multiple tracks along the direction of the magnetic nanoribbon A storage unit, each storage unit stores a magnetic skyrmion; the information reading part is used to read the polarity of the magnetic skyrmion passing therethrough.

The invention discloses a data encryption / decryption method based on a racetrack memory, comprising the following steps: dividing a racetrack memory array into a plurality of encryption areas with preset size as basic units of encryption storage, and setting an independent encryption key Shift-key for each encryption area; when a system is initialized, generating a Shift-key based on a random number for each storage area as an encryption key of the storage area, and storing the Shift-keys in a volatile static random access memory; after the keys are generated, performing shift encryption on each storage area according to the key; and when data is read or written, performing encryption / decryption on each storage area according to the key. The data encryption / decryption method can better protect data in the racetrack memory, ensure the security of data and avoid potential safety hazards caused by power failure or physical power stealing of the system. The invention further discloses a data encryption / decryption system based on a racetrack memory.

The invention discloses a quota control temperature based racetrack memory chip and a control method therefor. The racetrack memory chip comprises a substrate, racetrack memory strips, a filling layer and a heat dissipation apparatus. A mobile quota is set in a program running interval, so that hot spot dispersion is performed in time; and moreover, a data block is stored in the non-adjacent racetrack memory strips, so that hot spot dispersion is performed in space. The invention provides a control method for a temperature rise of a racetrack memory due to mobile operation. The method comprehensively considers hot spot diffusion in time and space, so that the temperature rise of the chip can be reduced as far as possible; and due to analog display, the performance loss caused by the method is only 5% averagely.

A computing in-memory system and computing in-memory method based on a skyrmion race memory are provided. The system comprises a circuit architecture of SRM-CIM. The circuit architecture of the SRM-CIM comprises a row decoder, a column decoder, a voltage-driven, a storage array, a modified sensor circuit, a counter Bit-counter and a mode controller. The voltage-driven includes two NMOSs, and the two NMOSs are respectively connected with a selector MUX. The modified sensor circuit compares the resistance between a first node to a second node and a third node to a fourth node by using a pre-charge sense amplifier. The storage array is composed of the skyrmion racetrack memories. The computing in-memory architecture is designed by utilizing the skyrmion racetrack memory, so that storage is realized in the memory, and computing operation can be carried out in the memory.

The invention provides a data programming method, a memory control circuit unit and a memory storage device. The method comprises the steps of setting a first class entity erasing unit as a current writing-in region and recording the current writing-in data size. The method further comprises the step of calculating a data size threshold value according to the first class entity erasing unit. The method further comprises the step of receiving data. The method further comprises the steps of adopting a first programming mode for programming the data to at least one first class entity erasing unit if the current writing-in data size is smaller than the data size threshold value; setting a second class entity erasing unit as a current writing-in region if the current writing-in data size is not smaller than the data size threshold value, and adopting a second programming mode for programming the data into at least one second class entity erasing unit. The problem that a rewritable type racetrack memory module cannot be used due to the fact that the erasing frequency of some entity erasing units is excessively large can be avoided.

A system including a racetrack memory layer is described. The racetrack memory layer includes a plurality of bit locations and a plurality of domain wall traps. The bit locations are interleaved with the domain wall traps. Each of the bit locations has a first domain wall speed. Each of the domain wall traps has a second domain wall speed. The first domain wall speed is greater than the second domain wall speed. The first domain wall speed and the second domain wall speed are due to at least one of a Dzyaloshinskii-Moriya interaction variation in the racetrack memory layer, a synthetic antiferromagnetic effect variation in the racetrack memory layer, and a separation distance for the plurality of domain wall traps corresponding to an intrinsic travel distance. The separation distance is less than one hundred nanometers.

A racetrack-type memory storage device that moves domain walls along the racetrack in only one direction. The reading unit can be placed at one end of the runway (rather than in the middle of the runway). Once the domain walls are moved across the read member, the domain walls disappear, but their corresponding information is read into one or more memory devices (eg, built-in CMOS circuits). The information can then be processed in circuitry for computational needs and written to either in its original form (eg, read from the racetrack) using a writing component placed on the opposite end of the racetrack from the reading component. out) or written back to the runway in a different form after some calculation. Such racetracks are simpler to construct and have higher operational reliability than previous racetrack-type memory devices.

The present invention is directed towards a tubular nanosized magnetic wire, wherein the nanosized magnetic wire comprises: a tubular magnetic shell surrounding a longitudinal axis of the wire, at least one region of the tubular magnetic shell is capable of providing a 360° magnetic domain wall, wherein the 360° magnetic domain wall is self-stabilizing and has a magnetization going from a parallel alignment to a perpendicular alignment and to a parallel alignment with regards to the wire axis. The present invention also provides a practical method capable of making a tubular nanosized magnetic wire with a self-stabilizing, 360° magnetic domain wall. The present invention also relates to the use of the tubular nanosized magnetic wire in a racetrack memory device.

The invention discloses a coding method of a racetrack storage position error correcting code and an error correcting method. The coding method of the correcting code comprises the steps of coding positions of one or more read-only access ends of a racetrack memory stripe (RS) relative to the RS as circulating codes, storing the circulating codes into the RS, enabling the position of the RS to correspond to partial circulating codes read from the RS at the moment, obtaining a position code by virtue of the circulating codes, and utilizing the position code as an error correcting code of the racetrack storage position. The circulating code is set as a continuous sequence of a plurality of circulating units, and the bit number of each circulating unit is one or more bits. According to the error correcting method, the error-type position error can be detected and corrected by comparing the position code stored in the access end position of a register and a position code obtained by decoding the circulating codes stored in the racetrack storage stripe, so that the problem of the error of the error-type position can be effectively solved.

The invention discloses a magnetic domain wall writing unit and method based on a multiferroic heterogeneous structure, comprising: a bottom electrode layer connected to a pulse voltage source; a piezoelectric layer made of ferroelectric material and arranged on the bottom electrode layer ; The top electrode layer is arranged on the piezoelectric layer, including a number of top electrodes connected to the pulse voltage source; the magnetic layer is on the same layer as the top electrode, made of ferromagnetic material, and connected to the track memory; wherein the iron of the magnetic layer Magnetic materials have magnetic anisotropy and have magnetostrictive properties. Apply pulse voltage to the top electrode and bottom electrode layer to generate strain in the piezoelectric layer, the strain is transmitted to the magnetic layer and induces magnetic domain walls, and the magnetic domain walls are driven to the track memory; adjust the pulse voltage to change the strain of the piezoelectric layer level, and then write different data. The invention utilizes the inverse piezoelectric effect and the inverse effect of magnetostriction to realize high storage density and low power consumption magnetic domain wall writing.