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Laminated chip packaging structure

A chip packaging structure, chip technology, applied in the direction of semiconductor/solid-state device parts, semiconductor devices, electrical components, etc., can solve the problems of limiting the flexibility of electrodes on the chip, large packaging area, low integration, etc., to achieve more packaging design It has the advantages of flexibility, small package structure area and high integration

Active Publication Date: 2016-04-13
HEFEI SMAT TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, the packaging area of ​​this stacked chip packaging structure is large, the integration level is low, and the flexibility of packaging design is low, which limits the flexibility of the layout of electrodes on the chip.

Method used

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  • Laminated chip packaging structure
  • Laminated chip packaging structure

Examples

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Effect test

Embodiment 1

[0036] figure 1 It is a cross-sectional view of a stacked chip package structure according to Embodiment 1 of the present invention.

[0037] refer to figure 1 As shown, the stacked chip package structure 01 mainly includes a chip 11 , a chip 21 , a rewiring component 31 and a plastic package 41 .

[0038] Among them, the chip 11 and the chip 21 both include the opposite active surface and the back surface, and both the chip 11 and the chip 21 include devices that have been fabricated, such as diodes, metal oxide field effect transistors (MOSFETs), insulated gate bipolar Active devices such as transistors (IGBTs). The active devices in the general chip include various active regions formed in the chip and pads exposed on the active surface of the chip. Such pads are electrode pads of the active devices in the chip, and can also be directly become the input and output terminals of electrodes or chips, for example, at least some of the pads 111 located on the active surface o...

Embodiment 2

[0047] figure 2 It is a cross-sectional view of the stacked chip package structure according to the second embodiment of the present invention.

[0048] refer to figure 2 As shown, the stacked chip package structure 02 includes a chip 12 , a chip 22 , a redistribution component 32 and a plastic package 42 .

[0049] The chip 12 and the chip 22 are the same as in the first example, and the devices on the active surface of the chip 22 are electrically connected to the pads 121 on the active surface of the chip 12 through the conductive bumps 221 .

[0050] In this embodiment, the rewiring component 32 also includes a first component 321 , a second component 322 and a third component 323 . One end of the first component 321 is electrically connected to the pad 121, and the other end extends to the second component 322 in the first direction, and the second component 322 extends in the second direction to serve as a redistribution layer of the stacked chip package structure 01...

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Abstract

The invention provides a laminated chip packaging structure. According to the laminated chip packaging structure, the active surfaces of an upper chip layer and a lower chip layer are opposite; electrodes on the lower chip layer are led to the surface of the laminated chip packaging structure to be re-arranged by a re-wiring part; electrodes of the upper chip layer are electrically connected to bonding pads of the lower chip layer through conductive bumps, and are led to the surface of the laminated chip packaging structure to be re-arranged by the re-wiring part; and the lower chip layer is supported by the upper chip layer. Therefore, the laminated chip packaging structure does not require a pre-established lead frame, and is provided with the re-wiring part, so that the packaging design is more flexible, the packaging area can be smaller, and the integration level can be higher.

Description

technical field [0001] The invention relates to the technical field of chip packaging, in particular to a stacked chip packaging structure. Background technique [0002] Chip packaging is the process of encapsulating a chip in an encapsulation material, thereby isolating the semiconductor material from the external environment and providing an electrical connection to an external circuit. The packaged components formed after the chip packaging process are chip products that can be sold in the market. [0003] With the improvement of people's demand for the integration of integrated circuits, the integration and packaging of multiple chips in packaging materials has become a research hotspot at this stage. An existing common stacked chip package structure usually includes a pre-designed lead frame, and the electrodes on the upper and lower chips in the stacked chip package structure are connected to the leads of the lead frame through conductive bumps or bonding wires. elec...

Claims

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Application Information

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IPC IPC(8): H01L23/482H01L23/488
CPCH01L24/09H01L24/10H01L2224/02373H01L2224/02381H01L2224/16225H01L2224/16145H01L2224/04105H01L2924/18162H01L2924/18161H01L2224/73209
Inventor 尤文胜
Owner HEFEI SMAT TECH CO LTD
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