Package structure and method of fabricating the same

Abstract

A package structure and a method for fabricating a package structure are provided. The method includes the steps of forming a wiring layer on a carrier by electroplating; disposing at least one electronic component on the wiring layer; forming on the carrier an insulating layer that encapsulates the wiring layer and the electronic component; and removing the carrier. With the single wiring layer having one surface electrically connected the at least one electronic component and the other surface electrically connected to a plurality of conductive elements, the package structure has a signal transmission path that is shortened.

Description

technical field [0001] The invention relates to a package structure, in particular to a package structure of a single-layer circuit layer and a manufacturing method thereof. Background technique [0002] With the development of semiconductor packaging technology, in smart phones, tablets, networks, notebook computers and other products, semiconductor devices have developed different packaging types, such as ball grid array (BGA), square Flat semiconductor package (Quad-FlatPackage, referred to as QFP) or quad flat non-lead type (QuadFlatNonleadPackage, referred to as QFN) semiconductor package, etc. [0003] Such as Figure 1A As shown, the existing QFP package structure 1 includes: a bearing base 10, a plurality of guide pins 11 located around the bearing base 10, bonded to the bearing base 10 and electrically connected to the guide pins 11 with a plurality of welding wires 120 The electronic component 12 and the insulating layer 13 such as encapsulant covering the electro...

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Problems solved by technology

[0009] However, in the existing BGA package structure 1', the electrical performance cannot be improved due to the long signal transmission path (ie, the conductive element 14, the circuit layers 11a, 11b, and the conductive pillar 100) when used at a higher frequency or at a high speed. , so that the performance of the package structure 1' is limited

[0010] In addition, the existing BGA package structure 1' needs to make at least two layers of circuit layers 11a, 11b and conductive pillars 100 (such as drilling process, and copper is plated in the via holes as the connection between layers), Therefore, the overall structure is difficult to meet the thinning requirements, and it is difficult to reduce the manufacturing cost due to the complex and long production process

[0011] Moreover, the existing BGA package structure 1' needs to make more connection interfaces (such as between the conductive elements 14, the circuit layers 11a, 11b and the conductive pillars 100), and it is necessary to use a composite carrier board 10 with different materials for each layer. ', so a substantial increase in manufacturing cost

[0012] In addition, since the carrier board 10' is made of multiple layers (composed of various raw materials) materials whose thermal expansion coefficient (CTE) does not match the electrical properties, especially the CTE mismatch between the materials, it is easy to process during the manufacturing process. warped

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