3D nonvolatile memory, and manufacturing method and power consumption reduction method thereof

Abstract

The invention discloses an FDSOI-process-based 3D nonvolatile memory, and a manufacturing method. The 3D nonvolatile memory comprises a silicon substrate, a buried oxide layer, a monocrystalline silicon top layer and a 3D nonvolatile memory storage array. The buried oxide layer serves as an insulation layer of the first layer and the third layer. The monocrystalline silicon top layer is used for realizing a peripheral CMOS logic circuit of the 3D nonvolatile memory. According to the invention, the two parts, being the 3D nonvolatile memory storage array and the peripheral CMOS logic circuit of the D nonvolatile memory, of the FDSOI-process-based 3D nonvolatile memory can be produced by different manufacturing works. The performances and power consumption of the 3D nonvolatile memory can be optimized by adjusting back gate voltages of different functional modules. The break-over voltage of the transistor can be reduced by adjusting the back gate voltages, so that the transistor can work normally under a lower voltage and even can work normally under a voltage close to a threshold voltage and thus the chip power consumption can be substantially reduced.

Description

technical field [0001] The invention relates to a 3D nonvolatile memory, in particular to a 3D nonvolatile memory based on an FDSOI process, a manufacturing method thereof, and a method for reducing power consumption. Background technique [0002] As the process nodes become smaller and smaller, the miniaturization process of memory chips is facing its limit. In order to obtain higher storage density and read speed, major manufacturers have gradually invested in the development of 3D memory technology. The feature of 3D memory technology is not realized by chip stacking or 3D packaging, but the storage unit adopts 3D technology. For example, in the traditional planar NAND flash memory, the floating gate transistor of the storage unit is a planar transistor, and all the source terminals and the drain terminals are located on the same plane, while the 3D-NAND storage unit uses a three-dimensional transistor, and the source terminals and the drain terminals are respectively in...

AI Technical Summary

Problems solved by technology

However, the use of DVFS technology requires the addition of many additional logic control circuits, which makes the entire 3D memory chip more complicated and the chip area will increase, resulting in higher production costs for 3D memory.

Images