SRAM

Abstract

The invention discloses a static random access memory, which comprises a first bit line, a first transistor, N memory cells, n second transistors, N first word lines, a second bit line, N third transistors, a third bit line, N fourth transistors and N second word lines, wherein the first transistor is connected between the first bit line and a power supply or ground through a source electrode and a drain electrode; each memory cell in the N memory cells is used for storing a level state, wherein the level state comprises a high level and a low level, and N is greater than or equal to 1; the N second transistors correspond to the N memory cells one by one; the N first word lines correspond to the N second transistors one by one, each word line in the N first word lines is connected to the grid electrode of the corresponding second transistor for controlling to read the level state from the corresponding memory cell; and the N second word lines correspond to the N fourth transistors and the N third transistors one by one. The static random access memory solves the problem of low stability of the data reading operation of the static random access memory.

Description

technical field [0001] The present application relates to the field of memory, in particular, to a static random access memory. Background technique [0002] Static Random Access Memory (SRAM) enables fast read / write operations. figure 1 It is a schematic diagram of a 6T SRAM according to the prior art, such as figure 1 As shown, each storage module of the 6T SRAM includes 6 transistors, namely transistor PG-1, transistor PG-2, transistor PU-1, transistor PD-1, transistor PU-2 and transistor PD-2. Transistor PU-1, transistor PD-1, transistor PU-2, transistor PD-2, power supply VDD and ground VSS together constitute a storage unit for storing level states, that is, high level states and low level states. The unit includes two storage nodes, which are storage node Q and storage node QN respectively, and storage node Q and storage node QN store a pair of opposite level states. The word line WL is connected to the gates of the transistor PG- 1 and the transistor PG- 2 , and i...

AI Technical Summary

Problems solved by technology

[0012] The embodiment of the present application provides a static random access memory to solve the problem of low stability of the data read operation of the static random access memory

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