Array package-based FPGA (field programmable gate array) chip

Abstract

The invention provides an array package-based FPGA (field programmable gate array) chip. Outermost two circles of pins of the FPGA chip are I / O (input / output) pins, an outermost row of the I / O pins and a secondarily outermost row of I / O pins form differential pairs in a longitudinal direction, and an outermost column of the I / O pins and a secondarily outermost column of the I / O pins form differential pairs in a transverse direction. The invention enables easier I / O fan-out and reduces the quantity of PCB (printed circuit board) design layers; meanwhile, a filter capacitor of an I / O power supply is easier and more reasonable to place, with better filtration effect.

Description

technical field [0001] The invention relates to the technical field of integrated circuit design, in particular to an FPGA chip based on array packaging. Background technique [0002] FPGA (Field Programmable Gate Array, Field Programmable Gate Array), as a semi-custom circuit in the field of application-specific integrated circuits, not only solves the shortcomings of custom circuits, but also overcomes the shortcomings of the limited number of original programmable device gates. With the development of FPGA technology, the number of I / Os continues to increase. At present, most FPGA chips are packaged in BGA (BallGridArray, solder ball array package). The number of pins in this package ranges from dozens to as many as More than a thousand, and most of the I / O can be used in differential pairs. The FPGA chip generally has several groups (BANK), and the voltage value of the I / O power supply of each group is the same. To obtain better signal integrity on the I / O, the I / O powe...

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Problems solved by technology

[0004] The outermost pin arrangement of the traditional BGA-packaged FPGA chip is irregular, and the influence of the arrangement of the pads on the fan-out of the I / O and the layout of the filter capacitor of the I / O power supply during PCB board-level design is not fully considered. , often resulting in difficulty in I / O fan-out in PCB board-level design or the need to increase the number of PCB layers to fan out all I / O, and the placement of filter capacitors for I / O power supplies is also difficult

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