Bus structure of SoC system

Abstract

The invention relates to the field of computers and discloses a bus structure of an SoC system. In the present invention, include: system bus (hereinafter referred to as sys_bus), dynamic memory access bus (hereinafter referred to as dram_bus), static memory access bus (hereinafter referred to as sram_bus); dram_bus and sram_bus are connected to sys_bus respectively, and sys_bus hangs connected to the embedded processor; the dynamic random access memory DRAM is mounted on the dram_bus, and the first type of module mounted on the dram_bus directly accesses the DRAM; the static random access memory SRAM is mounted on the sram_bus, and is mounted on the The second type of module on the sram_bus directly accesses the SRAM; among them, the data access capacity requirement of the first type module is greater than the data access capacity requirement of the second type module, and the data response rate of the second type module The speed requirement of is higher than the speed requirement of the data response rate of the first type of module. Embodiments of the present invention can provide a bus architecture for large-scale systems that require high transmission rates and have high-efficiency transmission characteristics.

Description

technical field [0001] The invention relates to the field of computers, in particular to a bus structure for an SoC system layered on demand. Background technique [0002] System on Chip ("SoC system") based on the Advanced Microcontroller Bus Architecture ("AMBA") protocol currently occupies a dominant position in the field of terminal chips sensitive to performance and power consumption. Its performance, cost, power consumption, and reliability It also has obvious advantages in terms of life cycle and applicability, and is also the direction of integrated circuit development. Among them, the bus architecture and performance directly affect the performance and efficiency of the entire SoC system. Choosing a reasonable and efficient bus architecture is the most important factor in designing a high-speed SoC system. one. [0003] An SoC bus system must be able to ensure reliable access between processors and other sub-modules. The following points are the two most basic prin...

AI Technical Summary

Problems solved by technology

In the existing technology, there is a bandwidth mismatch at both ends of the many-to-one bus, and the bandwidth and efficiency of the bus itself lead to low efficiency and performance degradation of the entire SoC system

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