Improvement method for dislocation defect in embedded SiGe epitaxy

Abstract

The invention provides an improvement method for a dislocation defect in embedded SiGe epitaxy. The improvement method comprises the following steps of firstly, appropriately reducing germanium concentration within a certain growth thickness range of a SiGe thin film during the reaction process of the SiGe epitaxy; secondly, gradually increasing the germanium concentration, and forming a linear concentration gradient until the average germanium concentration is exceeded; and finally, maintaining constant germanium concentration so as to complete growth. Compared with the prior art, the dislocation defect of the SiGe thin film induced by lattice mismatching caused by direct change of the germanium concentration during the growth process of the embedded SiGe epitaxy is reduced, the SiGe stress is improved, and the electrical property of a P-channel metal oxide semiconductor (PMOS) transistor is improved.

Description

technical field

[0001] The invention relates to the technical field of preparation of embedded silicon germanium epitaxy, in particular, the invention relates to a method for improving dislocation defects of embedded silicon germanium epitaxy. Background technique

[0002] It is well known that the performance of CMOS circuits is largely constrained by PMOS transistors. Therefore, any technology that can improve the performance of PMOS to the level of NMOS is considered beneficial. In 90nm PMOS, Intel engineers etched and removed the source and drain of the device, and then redeposited a silicon germanium (SiGe) layer, so that the source and drain would generate a compressive stress on the channel, thereby improving the PMOS performance. transfer characteristics.

[0003] figure 1 It is a PMOS structure of germanium-silicon source / drain implantation-induced strain technology in the prior art. Such as figure 1 As shown, silicon germanium source / drain implantation-induced...

Images