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A bonded wafer structure and its preparation method

A wafer and bonding technology, used in semiconductor/solid-state device manufacturing, electrical components, electrical solid-state devices, etc., can solve reliability problems, complicated follow-up processes, affect the thickness of the barrier layer, etc., to prevent reliability problems, The effect of enhancing reliability

Active Publication Date: 2018-08-24
WUHAN XINXIN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, with the increase of wafer integration, the follow-up process of UTS has also become complicated, and these follow-up processes have brought many reliability problems to the UTS itself (especially the top)
For example, the subsequent CMP process of UTS will affect the thickness of the barrier layer (blocklayer), and when the barrier layer is thin, reliability problems will occur, which is what those skilled in the art are unwilling to see

Method used

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  • A bonded wafer structure and its preparation method
  • A bonded wafer structure and its preparation method
  • A bonded wafer structure and its preparation method

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Embodiment 1

[0037] The invention discloses a bonded wafer structure. The bonded wafer structure includes a bonded wafer, a UTS structure arranged in the bonded wafer, and an upper surface of the UTS structure arranged on the bonded wafer. The barrier layer to be covered, the first oxide layer disposed on the barrier layer, the light-blocking metal layer disposed on the first oxide layer, and the light-blocking metal layer disposed on the first oxide layer and covering the light-blocking metal layer The second oxide layer; wherein, the bonded wafer is provided with a first metal layer and a second metal layer that are not in contact with each other, and the vertical projections of the first metal layer and the second metal layer on the same horizontal plane do not overlap each other or only Partial overlap; the UTS structure electrically connects the first metal layer and the second metal layer; the bonded wafer structure in the present invention strengthens the reliability of the UTS struc...

Embodiment 2

[0044] Such as figure 2 As shown, this embodiment discloses a method for preparing a bonded wafer structure, which specifically includes:

[0045] Step 1, providing a bonded wafer, the bonded wafer is provided with a first metal layer 23 and a second metal layer 13 that are not in contact with each other, and the first metal layer 23 and the second metal layer 13 are vertically on the same horizontal plane The projections do not overlap each other or overlap only partially; as in image 3 structure shown.

[0046] In an embodiment of the present invention, the specific steps of forming the bonded wafer are:

[0047] First, a first wafer and a second wafer to be processed are provided, and the first wafer includes a first substrate 21 and a first BEOL dielectric layer 22; the second wafer includes a second substrate 11 and a second BEOL dielectric Layer 12.

[0048]Secondly, the first wafer and the second wafer are face-to-face bonded together by hybrid bonding process or ...

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Abstract

The invention relates to the technical field of semiconductor manufacturing, and in particular to a bonded wafer structure and a preparation method thereof. The reliability of the UTS structure is enhanced by retaining a light-blocking metal layer above the UTS structure, so as to prevent insufficient tape of the blocking layer above the UTS structure. It can be realized without adding additional masks, which lays the foundation for the wider application of UTS structure in 3D integration.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a bonded wafer structure and a preparation method thereof. Background technique [0002] With the miniaturization and thinning of electronic devices and memories, there are higher requirements for the volume and thickness of chips. The three-dimensional integration of wafers is a solution to improve chip performance while maintaining the existing technology nodes. This technology integrates two or more chips with the same or different functions through bonding. This integration maintains the chip volume. At the same time, the performance of the chip is improved; at the same time, the metal interconnection between the functional chips is shortened, so that the heat generation, power consumption, and delay are greatly reduced; and the bandwidth between the functional modules is greatly improved, so as to maintain the existing technology nodes While improving th...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/60
CPCH01L24/03H01L24/07H01L24/09H01L24/82H01L24/94
Inventor 胡思平朱继锋董金文严孟
Owner WUHAN XINXIN SEMICON MFG CO LTD