Semiconductor device, manufacturing method therefor, and electronic device

Abstract

The invention relates to a semiconductor device, a manufacturing method, and an electronic device. The method comprises the steps: S1, providing a semiconductor substrate, and forming a virtual grid structure on the semiconductor substrate, wherein the virtual grid structure comprises a virtual grid dielectric layer; S2, depositing a first interlayer dielectric layer on the semiconductor substrate till the first interlayer dielectric layer reaches the a part below the top of the virtual grid structure; S3, forming a second interlayer dielectric layer on the first interlayer dielectric layer till the second interlayer dielectric layer reaches the a part above the top of the virtual grid structure, wherein the second interlayer dielectric layer and the virtual grid dielectric layer have a bigger etching selection ratio; S4, executing a flattening step till the virtual grid structure, and then removing the virtual grid structure. The method not only can reduce the loss of the interlayer dielectric layers in a process of removing a virtual grid electrode, but also can avoid a groove in a flattening process, and further improves the performance and yield of the semiconductor device.

Description

technical field [0001] The present invention relates to the field of semiconductors, in particular, the present invention relates to a semiconductor device, a preparation method thereof, and an electronic device. Background technique [0002] With the continuous development of semiconductor technology, the improvement of integrated circuit performance is mainly achieved by continuously reducing the size of integrated circuit devices to increase its speed. At present, the semiconductor industry pursuing high device density, high performance and low cost has advanced to the nanotechnology process node, especially when the size of semiconductor devices is reduced to a lower nanometer level, the preparation of semiconductor devices is limited by various physical limits. [0003] When the size of the semiconductor device is reduced to a lower nanometer level, the gate critical dimension (gateCD) in the device is correspondingly reduced to 24nm. With the reduction of technology n...

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Problems solved by technology

[0005] With the continuous shrinking of semiconductor devices, how to reduce the loss of the interlayer dielectric layer in the process of removing the dummy gate in the above method, and how to avoid the occurrence of grooves in the planarization of the interlayer dielectric layer, obtain Flat surfaces become a huge challenge in the fabrication of logic devices

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