A Subclock Ultrashort Pulse Generator
A technology of ultra-short pulse and generator, which is applied in the direction of electric pulse generator circuit, pulse generation, pulse technology, etc. It can solve the problems of complex system structure and pulse width cannot be arbitrarily modulated, and achieve strong detection ability and high consistency performance and reproducibility, high practical value
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example 1
[0038] Example 1: Electrical pulse at 200Mhz repetition rate with a pulse duration of 1 / 90
[0039] List the parameters of this embodiment 1 processing data here:
[0040] The clock module 100 adopts a 200Mhz active clock;
[0041] The phase-shifting module 200 adopts the digital clock manager of the FPGA to generate a phase-shifted clock of 90 degrees and a constant clock frequency;
[0042] The carry chain module 300 adopts a 90-order effective length carry chain (the actual length is 105 steps), and each stage of the carry chain is 5000 / 90 ps;
[0043] The combinatorial logic module 400 adopts the direct-connected buffer output for the carry chain fanout at the 1-45th order and the 47-90th order, and adopts the XOR logic of the 45th order and the 46th order at the 46th order fanout;
[0044] The coarse clock gating module 500 gates all pulses in a direct connection manner, that is, without adding any effective sequential logic.
example 2
[0045] Example 2: A 200Mhz clock source with a pulse duration of 1 / 90 Electrical pulses repeated at 10 ns intervals and 30 ns intervals
[0046] The parameters for processing data in this application instance 2 are listed here:
[0047] The clock module 100 adopts a 200Mhz active clock;
[0048] The phase-shifting module 200 adopts the digital clock manager of the FPGA to generate a phase-shifted clock of 90 degrees and a constant clock frequency;
[0049] The carry chain module 300 adopts a 90-order effective length carry chain (the actual length is 105 steps), and each stage of the carry chain is 5000 / 90 ps;
[0050]The combinatorial logic module 400 adopts the fan-out of the carry chain at the 1-45th order, the 47-65th order and the 67-90th order to adopt the direct connection buffer output, and adopts the XOR logic of the 45th order and the 46th order at the 46th order fan-out , the XOR logic of the 65th and 66th order carry chains is used in the 66th order fanout;
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example 3
[0052] Example 3: A 200Mhz clock source with a pulse duration of 1 / 90 Electrical pulses repeated at 10 ns intervals and 30 ns intervals
[0053] The parameters for processing data in this application instance 2 are listed here:
[0054] The clock module 100 adopts a 200Mhz active clock;
[0055] The phase-shifting module 200 adopts the digital clock manager of the FPGA to generate a phase-shifted clock of 90 degrees and a constant clock frequency;
[0056] The carry chain module 300 adopts a 90-order effective length carry chain (the actual length is 105 steps), and each stage of the carry chain is 5000 / 90 ps;
[0057] The combinatorial logic module 400 adopts the fan-out of the carry chain at the 1-45th order, the 47-65th order and the 67-90th order and adopts the direct connection buffer output, and the 46th-order combinatorial logic fan-out adopts the 45th-order and 46th-order different Or logic, the XOR logic of the 65th and 66th-order carry chains is used for the 66th-o...
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