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Method for layout pattern decomposition in electron beam and multi-pattern photoetching mixed process

A multi-pattern, electron beam technology, applied in electrical digital data processing, special data processing applications, instruments, etc., can solve problems such as the inability to obtain better solution quality

Active Publication Date: 2016-08-24
FUDAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

The advantage of this method is that the existing classic multi-pattern layout decomposition method can be reused; however, since the optimization of the number of multi-pattern stitching points and the use of electron beams are carried out independently in two stages, a better solution cannot be obtained quality
[0006] For the layout pattern decomposition method of the mixed process of electron beam and double pattern lithography, that is, in the case of K=2, the method based on primal-dual [10] can be used to simultaneously optimize the number of double pattern stitching points and the area used by the electron beam. However, The method based on primal-dual cannot be directly extended to the case of K>2, so if you want to solve the case of K>2, you need to redesign the method

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  • Method for layout pattern decomposition in electron beam and multi-pattern photoetching mixed process
  • Method for layout pattern decomposition in electron beam and multi-pattern photoetching mixed process
  • Method for layout pattern decomposition in electron beam and multi-pattern photoetching mixed process

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Embodiment 1

[0059] The pattern in the input layout file is as Figure 3.a As shown, it is necessary to decompose the layout pattern of the mixed process of electron beam and triple pattern (that is, K=3), where 1, 2, 3, 4, 5, and 6 are polygonal layout patterns, and the maximum number of iterations is set n r = 5, the number of consecutive no updates m = 3, the electron beam area weight α = 100, the sewing edge weight β = 1;

[0060] According to step 1.1, the Figure 3.a The polygon in is cut into several rectangles, such as Figure 3.b As shown, wherein, polygon 4 is cut into rectangle 41 and rectangle 42, and then the conflict graph is constructed according to the method described in step 1.2, the result is as follows Figure 3.c As shown in , where each rectangular pattern is represented as a corresponding vertex on the conflict graph, the solid line indicates that there are conflicting edges between the rectangles, and the dotted line indicates that there are candidate stitching po...

Embodiment 2

[0070] The second embodiment of the present invention is used to show that the method can obtain higher solution quality within a reasonable running time. In this embodiment, the number of multi-pattern photolithography masks is K=3, that is, triple pattern photolithography.

[0071] In this embodiment, a two-stage method is used as a comparison benchmark. The two-stage method first performs a multi-pattern layout decomposition, and then deletes a point set with a minimum weight to resolve conflicting edges that cannot be eliminated; method as a first-stage pattern decomposition solver for multi-pattern layouts.

[0072] The inventive method realizes with C++ programming language, and runs on the linux machine of a 64-bit 3.00GHz CPU and 4GB internal memory; The test layout comes from the first layer of metal layer layout in the ISCAS-85 & 89 test calculation example ; The minimum line width and minimum line spacing of the test layout in this embodiment are 30nm and 50nm resp...

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Abstract

The invention belongs to the technical field of integrated circuit semiconductor manufacturing and relates to a method for layout pattern decomposition in an electron beam and multi-pattern photoetching mixed process. According to the method, a layout pattern decomposition problem in minimizing an electron beam use area and a suture point number is represented as a deletion point K-partitioning problem. The method comprises the steps of according to input layout file and conflict distance B, constructing a conflict graph G; then randomly generating a deletion point K-partitioning initial solution and performing repeated iterative optimization on a current optimal solution by applying an existing deletion point two-partitioning algorithm until the current optimal solution is not updated for multiple times; and finally selecting an optimal deletion point K-partitioning result as an output. According to the method, the global optimal solution attempts to be searched for by iteratively applying the existing deletion point two-partitioning algorithm and adopting a random multi-initial-point policy, so that the purpose of layout pattern decomposition in the electron beam and multi-pattern photoetching mixed process is achieved.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit semiconductor manufacturing, and relates to a layout pattern decomposition method of electron beam and multi-pattern lithography hybrid process, especially a hybrid electron beam and multi-pattern with the area of ​​electron beam usage and the number of stitching points as optimization targets Pattern decomposition method for etching process layout. Background technique [0002] As the feature size of integrated circuits is further reduced and the complexity of chips continues to increase, the exposure resolution of traditional photolithography processes is approaching the physical limit, making it difficult to produce increasingly complex layout patterns. Research shows that next-generation lithography technologies such as extreme ultraviolet lithography (EUV), electron beam lithography (EBL) and multiple pattern lithography (Multiple Patterning Lithography, MPL) are gradually develope...

Claims

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Application Information

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IPC IPC(8): G06F17/50G06F9/44
Inventor 曾璇陆伟成周海严昌浩杨运峰
Owner FUDAN UNIV