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Method for preventing antenna effect of semiconductor chip layout

An antenna effect and semiconductor technology, applied in the field of semiconductor design and manufacturing, to achieve the effect of preventing antenna effect, saving area and simple structure

Active Publication Date: 2019-02-01
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

It can be seen that there must be enough area to insert a diode, and a diode is added to the layout. In order to pass the consistency check (LVS, Layout Versus schematic), a diode device must be added to the circuit. Although it does not affect the performance of the circuit, it is always More devices added

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  • Method for preventing antenna effect of semiconductor chip layout
  • Method for preventing antenna effect of semiconductor chip layout

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Embodiment Construction

[0020] In order to make the content of the present invention clearer and easier to understand, the content of the present invention will be described in detail below in conjunction with specific embodiments and accompanying drawings.

[0021] The invention belongs to a new method for preventing antenna effect in layout design. The invention makes full use of the mechanism of antenna effect, solves the problem through the generated mechanism, and considers the area of ​​the layout and the convenience of wiring at the same time, and finally obtains The invention provides a method for preventing the antenna effect of the semiconductor chip layout, which can not only save the area but also effectively prevent the antenna effect.

[0022] Specifically, during the chip production process, exposed metal wires or conductors such as polysilicon are like antennas, which will collect charges and cause the potential to rise. The longer the antenna, the more charge it collects and the high...

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Abstract

The invention provides a method for preventing an antenna effect in a semiconductor chip layout, and the method comprises the steps: employing a first device and a second device to form differential pair transistors, wherein the first and second devices are matched with each other; adding P-type heavily-doped regions to metal layers which are nearby the grid electrodes of the first and second devices and are the closest to a substrate, enabling the added P-type heavily-doped regions and a peripheral N well to form a parasitic diode, and enabling the grid electrodes of the first and second devices to be connected to the metal layers closest to the substrate through the P-type heavily-doped regions and polycrystalline silicon, thereby enabling charges to be released from the parasitic diode.

Description

technical field [0001] The invention relates to the field of semiconductor design and manufacture, more specifically, the invention relates to a method for preventing the antenna effect of the semiconductor chip layout. Background technique [0002] Currently, there are two common ways to prevent antenna effects on the layout. [0003] One is the "jumper method". The jumper is to disconnect the metal layer with antenna effect, connect to other layers through through holes, and finally return to the current layer. This method solves the antenna effect by changing the level of the metal wiring, but at the same time increases the via hole. Moreover, in the "jump wire method", since the resistance of the through hole is very large, it will directly affect the timing and crosstalk of the chip. Therefore, when using this method, the change of the wiring level and the number of through holes must be strictly controlled. Specifically, the antenna effect is that when a single layer...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/02
CPCH01L27/0292H01L27/0296
Inventor 朱静陈珏
Owner SHANGHAI HUALI MICROELECTRONICS CORP