Formation method of semiconductor structure

Abstract

The invention provides a method of forming a semiconductor structure, comprising the following steps: after a tunneling layer is formed on a semiconductor substrate, forming a first polycrystalline silicon layer doped with N-type ions on the tunneling layer; etching the first polycrystalline silicon layer on a memory area to form a floating gate layer; after a first insulating layer is formed on the floating gate layer, forming a second polycrystalline silicon layer on the semiconductor substrate, wherein the semiconductor second polycrystalline silicon layer covers the floating gate layer; and etching the second polycrystalline silicon layer, forming a control gate layer on the floating gate layer, and forming a selection gate layer at one side of the floating gate layer on the semiconductor substrate in the memory area, wherein there is a gap between the floating gate layer and the selection gate layer. Compared with the prior art, the manufacturing process of a split-gate flash memory of a shallow surface channel transistor structure is simplified effectively, and the manufacture difficulty and the process cost are reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure. Background technique [0002] Split-gate flash memory is a commonly used non-volatile semiconductor memory. With no over-erasing effect, relatively simple circuit design, and low-voltage, high-speed operation characteristics, it has become the mainstream technology of storage devices and is widely used in such as smart cards. , SIM cards, microcontrollers, mobile phones and other electronic products. [0003] refer to figure 1 As shown, a split-gate flash memory semiconductor substrate 10; a tunneling layer 11 on the semiconductor substrate 10, a floating gate 21 on the tunneling layer 11, an insulating layer 22 on the floating gate 21, and a floating gate 22 on the insulating The control gate 23 on the layer 22 , and the selection gate 24 on the tunneling layer 11 and on the side of the floating gate 21 and th...

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Problems solved by technology

[0018] As mentioned above, in the existing process of forming the floating gate and selection gate of the split-gate flash memory with shallow surface channel transistor structure, refer to Figure 5 and Image 6 , because after the intrinsic polysilicon layer 130 is formed on the semiconductor substrate, it is necessary to perform multiple ion implantation steps of different types into different regions of the intrinsic polysilicon layer, which are subsequently used to form N-type floating gates doped with different types of ions and P-type selection gate, and in multiple ion implantation steps, it is also necessary to perform multiple mask formation and removal steps on the intrinsic polysilicon layer, the existing manufacturing process of split-gate flash memory with shallow surface channel transistor structure Complicated and costly

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