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Semiconductor structures and methods of forming them

A semiconductor and gate structure technology, which is applied in the field of semiconductor structures and their formation, can solve problems such as poor performance of semiconductor structures, and achieve the goals of improving yield, reducing mismatch probability, and reducing threshold voltage floating difference and probability Effect

Active Publication Date: 2019-11-01
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0022] The problem solved by the present invention is: the performance of the semiconductor structure formed by the method of the prior art is not good

Method used

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  • Semiconductor structures and methods of forming them
  • Semiconductor structures and methods of forming them
  • Semiconductor structures and methods of forming them

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0078] First, combine the reference Figure 14 (a), 15(a) and 16(a), provide a semiconductor substrate, the semiconductor substrate includes an SRAM area I, the SRAM area I includes a first PMOS area A and a first NMOS area B, and the second A PMOS region A has a first fin 31a, and the first NMOS region B has a second fin 31b. The specific formation method is as follows:

[0079] The semiconductor substrate of the first PMOS region A includes a silicon substrate 301a having at least two discrete raised structures and an insulating layer 302a between the raised structures, the insulating layer 302a being lower than the raised structures. The raised structure higher than the insulating layer 302a is the first fin 31a.

[0080] The semiconductor substrate of the first NMOS region B includes a silicon substrate 301b having at least two discrete raised structures and an insulating layer 302b between the raised structures, the insulating layer 302b being lower than the raised stru...

Embodiment 2

[0133] The difference between embodiment two and embodiment one is:

[0134] combined reference Figure 14 to Figure 16 , the semiconductor substrate in Embodiment 1 further includes a logic region II, the logic region includes a second PMOS region C and a second NMOS region D, the second PMOS region C has a third fin 41a, and the second The NMOS region D has a fourth fin 41b.

[0135] The specific formation method is as follows:

[0136] The semiconductor substrate of the second PMOS region C includes a silicon substrate 401a having at least two discrete raised structures and an insulating layer 402a between the raised structures, the insulating layer 402a being lower than the raised structures 402a. The raised structure higher than the insulating layer 402a is the third fin 41a.

[0137] The semiconductor substrate in the second NMOS region D includes a silicon substrate 401b having at least two discrete raised structures and an insulating layer 402b between the raised stru...

Embodiment 3

[0195] The present invention provides a semiconductor structure, with reference to Figure 33 (a) and Figure 34 (a), including:

[0196] A semiconductor substrate having a SRAM region I comprising a first PMOS region A having a first fin 31a and a first NMOS region B having a first NMOS region B having a first fin 31a. two fins 31b;

[0197] a first gate structure across the first fin 31a, the first gate structure having a first work function layer;

[0198] a second gate structure across the second fin 31b, the second gate structure having a second work function layer;

[0199] The materials of the first work function layer and the second work function layer are the same.

[0200] In this embodiment, the first work function layer is a stack of the first work function material layer 81 on the bottom and the second work function material layer 82 on the top, or the second work function material layer 82, and the first work function material layer The material of the layer...

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Abstract

A semiconductor structure and a method of forming the same, wherein the method of forming the semiconductor structure includes: providing a semiconductor substrate, the semiconductor substrate including an SRAM region, the SRAM region including a first PMOS region and a first NMOS region; in the A first gate structure is formed on a semiconductor substrate in a PMOS region, and the first gate structure includes a first work function layer; a second gate structure is formed on a semiconductor substrate in a first NMOS region, and the second gate structure is formed on a semiconductor substrate in a PMOS region. The gate structure includes a second work function layer; the first work function layer and the second work function layer are made of the same material. The present invention is used to reduce the mismatch probability of the subsequently formed semiconductor structure and improve the yield of the subsequently formed semiconductor structure.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof. Background technique [0002] Static Random Access Memory (SRAM), as a member of memory, has the advantages of high speed, low power consumption and compatibility with standard processes, and is widely used in PCs, personal communications, consumer electronics (smart cards, digital cameras, Multimedia player) and other fields. [0003] A static random access memory includes a plurality of static random access memory units (hereinafter referred to as SRAM units), the plurality of SRAM units are arranged in an array, and a SRAM unit includes six transistors (6-T) electrically connected, specifically including two pull-up transistors , two pull-down transistors, and two pass transistors. Wherein, the pull-up transistor is a PMOS transistor, and the pull-down transistor and the pass transistor are NMOS transistors. ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/11H01L21/8244H10B10/00
CPCH01L21/823821H01L27/0924H01L29/7848
Inventor 李勇居建华
Owner SEMICON MFG INT (SHANGHAI) CORP
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