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A power device packaging structure and packaging method

A power device and packaging structure technology, which is applied in the manufacture of semiconductor devices, electrical solid state devices, and semiconductor/solid state devices, can solve the problems of low withstand voltage of external pins, poor thermal conductivity of device packaging, and small package chip size, etc., to achieve heat conduction Good performance, increased heat conduction area, and increased selectivity

Active Publication Date: 2018-11-23
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] The purpose of the present invention is to propose a solution to the problems of device damage caused by the parasitic inductance of the three-pin structure existing in the above-mentioned traditional power device packaging, the size of the packaged chip is small, the thermal conductivity of the device package is poor, and the withstand voltage of the outer pins is low. New four-pin, large chip and small package, pin high withstand voltage, good thermal conductivity power device packaging structure

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  • A power device packaging structure and packaging method
  • A power device packaging structure and packaging method
  • A power device packaging structure and packaging method

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Embodiment Construction

[0025] The specific embodiment of the present invention is described below in conjunction with accompanying drawing

[0026] Such as Figure 5 As shown, a packaging structure of a power device in the present invention includes a chip slot 1 , a metal casing 2 , an annular bonding layer 3 , four outer pins 4 , and a metal cover plate 5 . The size of the chip groove is 10*9*3mm, which is a traditional TO263-5L package ( image 3 The size of the chip slot 1 of ) should be large, and a chip with a larger volume can be placed to realize a large chip and a small package. The heat conduction area in the chip slot 1 is enlarged.

[0027] For the four-pin structure of some new power devices, especially power devices used in the pulse field, the traditional three-pin package no longer meets the packaging requirements of this type of chip, such as figure 1 As shown, if a three-pin package is used, for the IGBT chip used in the pulse discharge circuit, a large current will pass through...

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Abstract

The invention relates to a power device packaging structure, a packaging method and a packaging method. The power device packaging structure of the present invention includes a chip slot, a metal casing integrated with the chip slot that can be used as an electrode alone, and is fixed on the metal casing through an annular insulating layer. pins under the side of the fuselage, and a metal cover for device sealing. The metal tube shell of the present invention can be used as an independent electrode, and is welded in the circuit in the form of a patch; the four-tube leg structure of the package can meet the requirements of the new power device on the number of pins; it is similar to the traditional power device. Compared with the present invention, the chip slot for placing the chip is larger, and the outer tube shell made of metal is smaller in size, which can realize the large chip and small package of the high-power device.

Description

technical field [0001] The invention belongs to the technical field of semiconductor device packaging, and in particular relates to a power device packaging structure and a packaging method. Background technique [0002] Power semiconductor devices mainly refer to high-power electronic devices used in power conversion and control circuits of power equipment. Usually, the current is tens to thousands of amps, and the voltage reaches hundreds of volts. Currently commonly used power semiconductor devices include thyristors, GTOs, MOSFETs, IGBTs, etc. The package pins of these power devices need to withstand high withstand voltage or high current. Therefore, power device packages equipped with such high-power semiconductor chips need to have high resistance In addition, with the increase of power withstand voltage and current drive capability, the chip size is also increasing, and the packaging of new power devices also needs to have the ability to package large-size chips. [...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/367H01L23/48H01L23/31H01L23/495H01L21/50H01L21/60
CPCH01L2224/48091H01L2224/48247H01L2924/181H01L2924/00012H01L2924/00014
Inventor 陈万军刘亚伟唐血峰娄伦飞陶虹刘承芳刘杰张波
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA