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NAND flash memory array architecture having low read latency and low program disturb

A NAND flash and memory technology, applied in the field of NAND flash memory array architecture, can solve the problems of long read delay time and limitation, achieve low power consumption, reduce read delay, and high memory density Effect

Active Publication Date: 2016-12-07
WINBOND ELECTRONICS CORP
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  • Abstract
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Problems solved by technology

Unfortunately, because NAND flash memory often has a long read latency (read latency time), the NAND flash memory is limited in applications that require random access and continuous page reading

Method used

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  • NAND flash memory array architecture having low read latency and low program disturb
  • NAND flash memory array architecture having low read latency and low program disturb
  • NAND flash memory array architecture having low read latency and low program disturb

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Embodiment Construction

[0051] The illustrated embodiments or examples of the invention will be described as follows. The scope of the present invention is not limited thereto. Those skilled in the art should be able to understand that some modifications, substitutions and substitutions can be made without departing from the spirit and structure of the present invention. In the embodiments of the present invention, element symbols may be used repeatedly, and several embodiments of the present invention may share the same element symbols, but the characteristic elements used in one embodiment are not necessarily used in another embodiment.

[0052] In order to compete with NOR flash memory devices in specific applications, NAND flash memory devices should have the following characteristics, including: (1) Multiple input / output serial peripheral interface (SPI) or multiple input / output quad Peripheral interface (Quad Peripheral Interface, QPI); (2) Small size and low pin count package type (density as...

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Abstract

A NAND flash memory achieves low read latency and avoidance of inadvertent programming and program disturb so that the random access and initial page read speeds of the NAND flash memory are generally comparable to that of a NOR flash memory, while preserving the higher memory density and lower power operation characteristics of traditional NAND flash memory relative to NOR flash memory. The reduction in latency is achieved by a NAND memory array architecture which employs a small NAND string, a dual plane interleaved memory architecture, a partitioned NAND array, selectively coupled local bit lines per each global bit line, and a counter-biasing mechanism to avoid inadvertent programming and program disturb.

Description

technical field [0001] The present invention relates to digital memory devices and their operations, and more particularly to NAND flash memory array architectures with low read latency and low program disturbance. Background technique [0002] NAND flash memory is often used for data storage. In a density above 512 Mbits, the cost of a single level cell (Single Level Cell, “SLC”) NAND flash memory has a great advantage. This is due to the smaller size memory cells used in SLC-NAND flash memory itself. [0003] With the development of various technologies suitable for NAND flash memory, NAND flash memory is also often used in various applications other than data storage. Unfortunately, because the NAND flash memory often has a long read latency (read latency), the NAND flash memory is limited in applications that require random access and continuous page reading. Contents of the invention [0004] The present invention provides a NAND gate flash memory and its operation...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C16/06G11C16/26
CPCG11C7/18G11C8/12G11C16/26G11C16/0483G11C16/08G11C16/10
Inventor 李钟午安尼尔·古普特金大铉
Owner WINBOND ELECTRONICS CORP
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